DLPS081 February   2022 DLP3020-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

Over Section 6.4 unless otherwise noted.
MINNOMMAXUNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tSUSetup time SAC_BUS low before SAC_CLK↑1.0ns
tHHold time SAC_BUS low after SAC_CLK↑1.0ns
tSUSetup time DAD_BUS high before SAC_CLK↑1.0ns
tHHold time DAD_BUS after SAC_CLK↑1.0ns
tCCycle time SAC_CLK12.516.67ns
tWPulse width 50% to 50% reference points: SAC_CLK high or low5.0ns
tRRise time 20% to 80% reference points: SAC_CLK2.5ns
tFFall time 80% to 20% reference points: SAC_CLK2.5ns
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tSUSetup time DATA(14:0) before DCLK↑ or DCLK↓1.0ns
tHHold time DATA(14:0) after DCLK↑ or DCLK↓1.0ns
tSUSetup time SCTRL before DCLK↑ or DCLK↓1.0ns
tHHold time SCTRL after DCLK↑ or DCLK↓1.0ns
tSUSetup time TRC before DCLK↑ or DCLK↓1.0ns
tHHold time TRC after DCLK↑ or DCLK↓1.0ns
tSUSetup time LOADB low before DCLK↑1.0ns
tHHold time LOADB low after DCLK↓1.0ns
tSUSetup time RESET_STROBE high before DCLK↑1.0ns
tHHold time RESET_STROBE after DCLK↑3.5ns
tCCycle time DCLK12.516.67ns
tWPulse width 50% to 50% reference points: DCLK high or low5.0ns
tW(L)Pulse width 50% to 50% reference points: LOADB low7.0ns
tW(H)Pulse width 50% to 50% reference points: RESET_STROBE high7.0ns
tRRise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB2.5ns
tFFall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB2.5ns
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
fTCKClock frequency TCK10MHz
tCCycle time TCK100ns
tWPulse width 50% to 50% reference points: TCK high or low10ns
tSUSetup time TDI valid before TCK↑5ns
tHHold time TDI valid after TCK↑25ns
tSUSetup time TMS valid before TCK↑5ns
tHHold time TMS valid after TCK↑25ns
tRRise time 20% to 80% reference points: TCK, TDI, TMS2.5ns
tRFall time 80% to 20% reference points: TCK, TDI, TMS2.5ns
GUID-EA03F547-6C97-4E19-8097-7386E9450EB5-low.gifFigure 6-2 DMD Mirror and SRAM Control Logic Timing Requirements
GUID-6FB67375-FB31-41ED-A51C-423B63B503EF-low.gifFigure 6-3 DMD Data Path and Control Logic Timing Requirements
GUID-11E70F99-651A-426C-8E16-38DE774FC7EF-low.gifFigure 6-4 JTAG Boundary Scan Control Logic Timing Requirements