DLPS081 February   2022 DLP3020-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-D3982F46-F574-41E4-9A1D-E0AC2E316F38-low.gifFigure 5-1 FQR Package,64-Pin LGA(Bottom View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DATA(0) A2 LVCMOS input Data bus. Synchronous to rising edge and falling edge of DCLK.
DATA(1) A4
DATA(2) B2
DATA(3) B3
DATA(4) B5
DATA(5) C2
DATA(6) C3
DATA(7) B4
DATA(8) C5
DATA(9) D2
DATA(10) D3
DATA(11) D4
DATA(12) D5
DATA(13) E2
DATA(14) F5
DCLK F4 Data clock.
LOADB F3 Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK.
SCTRL E4 Serial control (sync). Synchronous to rising edge and falling edge of DCLK.
TRC F2 Toggle rate control. Synchronous to rising edge and falling edge of DCLK.
DAD_BUS B15 Reset control serial bus. Synchronous to rising edge of SAC_CLK.
RESET_OEZ C15 Active low. Output enable signal for internal reset driver circuitry.
RESET_STROBE B13 Rising edge on RESET_STROBE latches in the control signals.
SAC_BUS A15 Stepped address control serial bus. Synchronous to rising edge of SAC_CLK.
SAC_CLK A14 Stepped address control clock.
TCK F15 JTAG clock.
TDI E13 JTAG data input. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor.
TDO G15 LVCMOS output JTAG data output. Synchronous to falling edge of TCK. Tri-state fail-safe output buffer.
TMS G14 LVCMOS input JTAG mode select. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor.
TEMP_MINUS G13 Analog input Calibrated temperature diode used to assist accurate temperature measurements of DMD die.
TEMP_PLUS G2
VBIAS D15 Power Power supply for positive bias level of mirror reset signal.
VCC A5, B12, C14, D12, F13, G3 Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down.
VOFFSET E14 Power Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal.
VREF E15 Power supply for low voltage CMOS DDR interface.
VRESET D14 Power supply for negative reset level of mirror reset signal.
VSS A3, A13, B14, C4, C12, C13, D13, E3, E5, E12, F12, F14, G4, G12 Common return for all power.
RESERVED A1, A12, A16,B1, B16, F1, F16, G1, G5, G16 Reserved Do not connect.