DLPS081 February   2022 DLP3020-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(2)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH High level output voltage VCC = 2.25 V 1.7 V
IOH = –8 mA
VOH2 High level output voltage(6) VREF = 1.8 V 1.44 V
IOH = –2 mA
VOL Low level output voltage VCC = 2.75 V 0.4 V
IOL = 8 mA
VOL2 Low level output voltage(6) VREF = 1.8 V 0.36 V
IOL = 2 mA
IOZ Output high impedance current VREF = 1.95 V –10 µA
VOL = 0 V
VREF = 1.95 V 10
VOH = VREF
IIL Low level input current(3) VREF = 1.95 V –5 µA
VI = 0 V
IIH High level input current(3) VREF = 1.95 V 6 µA
VI = VREF
IIL2 Low level input current(4) VREF = 1.95 V –785 µA
VI = 0 V
IIH2 High level input current(4) VREF = 1.95 V 6 µA
VI = VREF
IIL3 Low level input current(5) VREF = 1.95 V –5 µA
VI = 0 V
IIH3 High level input current(5) VREF = 1.95 V 785 µA
VI = VREF
CURRENT
IREF Current at VREF = 1.95 V fDCLK = 80 MHz 2.80 mA
Icc Current at VCC = 2.75 V fDCLK = 80 MHz 59.90 mA
IOFFSET Current at VOFFSET = 8.75 V 2.93 mA
IBIAS Current at VBIAS = 16.5 V 2.30 mA
IRESET Current at VRESET = –10.5 V –2.00 mA
POWER
PREF Power at VREF = 1.95 V fDCLK = 80 MHz 5.46 mW
PCC Power at VCC = 2.75 V fDCLK = 80 MHz 164.73 mW
POFFSET Power at VOFFSET = 8.75 V 25.64 mW
PBIAS Power at VBIAS = 16.5 V 37.95 mW
PRESET Power at VRESET = –10.5 V 21.00 mW
PTOTAL Total power at nominal conditions fDCLK = 80 MHz 254.77 mW
CAPACITANCE
CIN Input pin capacitance ƒ = 1 MHz 20 pF
CA Analog pin capacitance (TEMP_PLUS and TEMP_MINUS pins) ƒ = 1 MHz 65 pF
Co Output pin capacitance ƒ = 1 MHz 20 pF
(1) All voltage values are with respect to the ground pins (VSS).
(2) Device electrical characteristics are over Section 6.4 unless otherwise noted.
(3) Specification is for LVCMOS input pins, which do not have pull up or pull down resistors. See Section 5.
(4) Specification is for LVCMOS input pins which do have pull up resistors (JTAG: TDI, TMS). See Section 5.
(5) Specification is for LVCMOS input pins which do have pull down resistors. See Section 5.
(6) Specification is for LVCMOS JTAG output pin TDO.