DLPS176A April   2019  – September 2019 DLP3034-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DLP DLP3034-Q1 Block System Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 Micromirror Array Temperature Calculation
    6. 7.6 Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
    4. 8.4 Illumination Mission Profile Considerations
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements

Over Recommended Operating Conditions unless otherwise noted.
MIN NOM MAX UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tSU Setup time SAC_BUS low before SAC_CLK↑ 1.0 ns
tH Hold time SAC_BUS low after SAC_CLK↑ 1.0 ns
tSU Setup time DAD_BUS high before SAC_CLK↑ 1.0 ns
tH Hold time DAD_BUS after SAC_CLK↑ 1.0 ns
tC Cycle time SAC_CLK 12.5 16.67 ns
tW Pulse width 50% to 50% reference points: SAC_CLK high or low 5.0 ns
tR Rise time 20% to 80% reference points: SAC_CLK 2.5 ns
tF Fall time 80% to 20% reference points: SAC_CLK 2.5 ns
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tSU Setup time DATA(14:0) before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time DATA(14:0) after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time SCTRL before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time SCTRL after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time TRC before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time TRC after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time LOADB low before DCLK↑ 1.0 ns
tH Hold time LOADB low after DCLK↓ 1.0 ns
tSU Setup time RESET_STROBE high before DCLK↑ 1.0 ns
tH Hold time RESET_STROBE after DCLK↑ 3.5 ns
tC Cycle time DCLK 12.5 16.67 ns
tW Pulse width 50% to 50% reference points: DCLK high or low 5.0 ns
tW(L) Pulse width 50% to 50% reference points: LOADB low 7.0 ns
tW(H) Pulse width 50% to 50% reference points: RESET_STROBE high 7.0 ns
tR Rise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB 2.5 ns
tF Fall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB 2.5 ns
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
fTCK Clock frequency TCK 10 MHz
tC Cycle time TCK 100 ns
tW Pulse width 50% to 50% reference points: TCK high or low 10 ns
tSU Setup time TDI valid before TCK↑ 5 ns
tH Hold time TDI valid after TCK↑ 25 ns
tSU Setup time TMS valid before TCK↑ 5 ns
tH Hold time TMS valid after TCK↑ 25 ns
tR Rise time 20% to 80% reference points: TCK, TDI, TMS 2.5 ns
tR Fall time 80% to 20% reference points: TCK, TDI, TMS 2.5 ns
DLP3034-Q1 timing_req_def_1.gifFigure 2. DMD Mirror and SRAM Control Logic Timing Requirements
DLP3034-Q1 timing_req_def_2.gifFigure 3. DMD Data Path and Control Logic Timing Requirements
DLP3034-Q1 jtag_timing_req.gifFigure 4. JTAG Boundary Scan Control Logic Timing Requirements