DLPS147B January   2019  – May 2022 DLP4500NIR

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Chipset Component Usage Specification
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
      3. 12.1.3 Device Markings
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Routing Constraints

In order to meet the specifications listed in the following tables, typically the PCB designer must route these signals manually (not using automated PCB routing software). In case of length matching requirements, routing traces in a serpentine fashion may be required. Keep the number of turns to a minimum and the turn angles no sharper than 45°. Traces must be 0.1 inches from board edges when possible; otherwise they must be 0.05 inches minimum from the board edges. Avoid routing long traces all around the PCB. PCB layout assumes adjacent trace spacing is twice the trace width. However, three times the trace width will reduce crosstalk and significantly help performance.

The maximum and minimum signal routing trace lengths include escape routing.

Table 11-4 Signal Length Routing Constraints for DMD Interface
SIGNALSMINIMUM SIGNAL ROUTING LENGTH(1)MAXIMUM SIGNAL ROUTING LENGTH(2)
DMD_D(23:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB,2480 mil
(63 mm)
2953 mil
(75 mm)
DMD_OE, DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_CLK, and DMD_SAC_BUS512 mil
(13 mm)
5906 mil
(150 mm)
Signal lengths below the stated minimum will likely result in overshoot or undershoot.
DMD-DDR maximum signal length is a function of the DMD_DCLK rate.

Each high-speed, single-ended signal should be routed in relation to its reference signal, such that a constant impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping total trace lengths to a minimum. The following signals should follow the signal matching requirements described in Table 11-5.

Table 11-5 High-Speed Signal Matching Requirements for DMD Interface
SIGNALSREFERENCE SIGNALMAX MISMATCHUNIT
DMD_D(23:0), DMD_TRC, DMD_SCTRL, DMD_LOADBDMD_DCLK±200
(±5.08)
mil
(mm)
DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_BUS, DMD_OEDMD_SAC_CLK±200
(±5.08)
mil
(mm)

The values in Table 11-5 apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC350 or DMD. Additional margin can be attained if internal DLPC350 package skew is taken into account. Additionally, to minimize EMI radiation, serpentine routes added to facilitate trace length matching should only be implemented on signal layers between reference planes.

Both the DLPC350 output timing parameters and the DMD input timing parameters include a timing budget to account for their respective internal package routing skew. Thus, additional system margin can be attained by comprehending the package variations and compensating for them in the PCB layout. To increase the system timing margin, TI recommends that the DLPC350 package variation be compensated for (by signal group), but it may not be desirable to compensate for DMD package skew. This is due to the fact that each DMD has a different skew profile, making the PCB layout DMD specific. To use a common PCB design for different DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB, or the package lengths for all applicable DMDs being considered. Table 11-6 provides the DLPC350 package output delay at the package ball for each DMD interface signal.

The total length of all the traces in Table 11-6 should be matched to the DMD_DCLK trace length. Total trace length includes package skews, PCB length, and DMD flex cable length.

Table 11-6 DLPC350 Package Skew and Routing Trace Length for the DMD Interface
SIGNALTOTAL DELAY (Package Skews)PACKAGE PIN
(ps)(mil)
DMD_D025.9152.35A8
DMD_D119.6115.29B8
DMD_D213.478.82C8
DMD_D37.443.53D8
DMD_D418.1106.47B11
DMD_D511.165.29C11
DMD_D64.425.88D11
DMD_D70.00.00E11
DMD_D814.887.06C7
DMD_D918.4108.24B10
DMD_D106.437.65E7
DMD_D114.828.24D10
DMD_D1229.8175.29A6
DMD_D1325.7151.18A12
DMD_D1419.0111.76B12
DMD_D1511.768.82C12
DMD_D164.727.65D12
DMD_D1721.5126.47B7
DMD_D1824.8145.88A10
DMD_D198.348.82D7
DMD_D2023.9140.59B6
DMD_D211.69.41E9
DMD_D2210.762.94C10
DMD_D2316.798.24C6
DMD_DCLK24.8145.88A9
DMD_LOADB18.0105.88B9
DMD_SCTRL11.467.06C9
DMD_TRC4.627.06D9
Table 11-7 Routing Priority
SIGNALROUTING PRIORITYROUTING LAYERMATCHING REFERENCE SIGNALTOLERANCE
DMD_DCLK(1) (2) (3)13
DMD_D[23:0], DMD_SCTRL, DMD_TRC, DMD_LOADB(1) (2) (3) (4)13, 4DMD_DCLK±150 mils
P1_A[9:0], P1_B[9:0], P1_C[9:0], P1_HSYNC, P1_VSYNC, P1_DATAEN, P1X_CLK13, 4P1X_CLK±0.1 inches
R[A-E]_IN_P, R[A-E]_IN_N, RCK_IN_P, RCK_IN_N23, 4RCK±150 mils
Differential signals need to be matched within ±12 mils
Total signal length from the DLPC350 and the DMD, including flex cable traces and PCB signal trace lengths must be held to the lengths specified in Table 11-4.
Switching routing layers is not permitted except at the beginning and end of a trace.
Minimize vias on DMD traces.
Matching includes PCB trace length plus the DLPC350 package length plus the DMD flex cable length.