DLPS147B
January 2019 – May 2022
DLP4500NIR
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Chipset Component Usage Specification
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Storage Conditions
7.3
ESD Ratings
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
Electrical Characteristics
7.7
Timing Requirements
7.8
System Mounting Interface Loads
7.9
Micromirror Array Physical Characteristics
7.10
Micromirror Array Optical Characteristics
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
8.4.1
Operating Modes
8.5
Micromirror Array Temperature Calculation
8.5.1
Package Thermal Resistance
8.5.2
Case Temperature
8.5.2.1
Temperature Calculation
8.6
Micromirror Landed-on/Landed-Off Duty Cycle
8.6.1
Definition of Micromirror Landed-On/Landed-Off Duty Cycle
8.6.2
Landed Duty Cycle and Useful Life of the DMD
8.6.3
Landed Duty Cycle and Operational DMD Temperature
8.6.4
Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
9
Applications and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
DLPC350 System Interfaces
9.2.2.1.1
Control Interface
9.2.2.1.2
Input Data Interface
9.2.2.2
DLPC350 System Output Interfaces
9.2.2.2.1
Illumination Interface
9.2.2.2.2
Trigger Interface (Sync Outputs)
9.2.2.3
DLPC350 System Support Interfaces
9.2.2.3.1
Reference Clock
9.2.2.3.2
PLL
9.2.2.3.3
Program Memory Flash Interface
9.2.2.4
DMD Interfaces
9.2.2.4.1
DLPC350 to DMD Digital Data
9.2.2.4.2
DLPC350 to DMD Control Interface
9.2.2.4.3
DLPC350 to DMD Micromirror Reset Control Interface
10
Power Supply Recommendations
10.1
Power Supply Sequencing Requirements
10.2
DMD Power Supply Power-Up Procedure
10.3
DMD Power Supply Power-Down Procedure
11
Layout
11.1
Layout Guidelines
11.1.1
DMD Interface Design Considerations
11.1.2
DMD Termination Requirements
11.1.3
Decoupling Capacitors
11.1.4
Power Plane Recommendations
11.1.5
Signal Layer Recommendations
11.1.6
General Handling Guidelines for CMOS-Type Pins
11.1.7
PCB Manufacturing
11.1.7.1
General Guidelines
11.1.7.2
Trace Widths and Minimum Spacings
11.1.7.3
Routing Constraints
11.1.7.4
Fiducials
11.1.7.5
Flex Considerations
11.1.7.6
DLPC350 Thermal Considerations
11.2
Layout Example
11.2.1
Printed Circuit Board Layer Stackup Geometry
11.2.2
Recommended DLPC350 MOSC Crystal Oscillator Configuration
11.2.3
Recommended DLPC350 PLL Layout Configuration
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.1.2
Device Nomenclature
12.1.3
Device Markings
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
FQD|98
MCLG010B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
dlps147b_oa
12
Device and Documentation Support