DLPS147B January   2019  – May 2022 DLP4500NIR

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
      3. 12.1.3 Device Markings
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
SUPPLY VOLTAGES (2)
VCCSupply voltage for LVCMOS core logic–0.54V
VREFSupply voltage for LVCMOS DDR interface–0.54V
VOFFSETSupply voltage for high voltage CMOS and micromirror electrode–0.58.75V
VBIAS (3)Supply voltage for micromirror electrode–0.517V
VRESETSupply voltage for micromirror electrode–110.5V
|VBIAS - VOFFSET| (3)Supply voltage delta (absolute value)8.75V
INPUT VOLTAGES (2)
Input voltage to all other input pins–0.5VREF + 0.5V
INPUT CURRENTS
Current required from a high-level outputVOH = 1.4 V–9mA
Current required from a low-level outputVOL = 0.4 V18mA
CLOCKS
fCLKDCLK clock frequency80120MHz
ENVIRONMENTAL
TCASECase temperature - operational (4)–2090°C
Case temperature - non-operational (4)–4090°C
TDPDew Point (operation and non-operational)81°C
Operating Relative Humidity (non-condensing)095%RH
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are referenced to common ground VSS. Supply voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(4) DMD Temperature is the worst-case of any test point shown in or Figure 8-3, or the active array as calculated by the Micromirror Array Temperature Calculation, or any point along the Window Edge as defined in or Figure 8-3. The locations of thermal test point TP2 is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.