DLPS229B December 2022 – August 2024 DLP4621-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE | SIGNAL | DATA RATE | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
DATA INPUTS | |||||
D_AN(0) |
A3 |
I | SubLVDS | Double | Data, Negative |
D_AN(1) |
B1 |
I | SubLVDS | Double | Data, Negative |
D_AN(2) |
C2 |
I | SubLVDS | Double | Data, Negative |
D_AN(3) |
F2 |
I | SubLVDS | Double | Data, Negative |
D_AN(4) |
H2 |
I | SubLVDS | Double | Data, Negative |
D_AN(5) |
K1 |
I | SubLVDS | Double | Data, Negative |
D_AN(6) |
K4 |
I | SubLVDS | Double | Data, Negative |
D_AN(7) |
K6 |
I | SubLVDS | Double | Data, Negative |
D_AP(0) | A2 | I | SubLVDS | Double | Data, Positive |
D_AP(1) |
C1 |
I | SubLVDS | Double | Data, Positive |
D_AP(2) |
D2 |
I | SubLVDS | Double | Data, Positive |
D_AP(3) |
E2 |
I | SubLVDS | Double | Data, Positive |
D_AP(4) |
G2 |
I | SubLVDS | Double | Data, Positive |
D_AP(5) |
K2 |
I | SubLVDS | Double | Data, Positive |
D_AP(6) |
K3 |
I | SubLVDS | Double | Data, Positive |
D_AP(7) |
K5 |
I | SubLVDS | Double | Data, Positive |
D_BN(0) |
A22 |
I | SubLVDS | Double | Data, Negative |
D_BN(1) |
B24 |
I | SubLVDS | Double | Data, Negative |
D_BN(2) |
D23 |
I | SubLVDS | Double | Data, Negative |
D_BN(3) |
F23 |
I | SubLVDS | Double | Data, Negative |
D_BN(4) |
H23 |
I | SubLVDS | Double | Data, Negative |
D_BN(5) |
K24 |
I | SubLVDS | Double | Data, Negative |
D_BN(6) |
K21 |
I | SubLVDS | Double | Data, Negative |
D_BN(7) |
K19 |
I | SubLVDS | Double | Data, Negative |
D_BP(0) |
A23 |
I | SubLVDS | Double | Data, Positive |
D_BP(1) |
C24 |
I | SubLVDS | Double | Data, Positive |
D_BP(2) |
C23 |
I | SubLVDS | Double | Data, Positive |
D_BP(3) |
E23 |
I | SubLVDS | Double | Data, Positive |
D_BP(4) |
G23 |
I | SubLVDS | Double | Data, Positive |
D_BP(5) |
K23 |
I | SubLVDS | Double | Data, Positive |
D_BP(6) |
K22 |
I | SubLVDS | Double | Data, Positive |
D_BP(7) |
K20 |
I | SubLVDS | Double | Data, Positive |
DCLK_AN |
J1 |
I | SubLVDS | Double | Clock, Negative |
DCLK_AP |
H1 |
I | SubLVDS | Double | Clock, Positive |
DCLK_BN |
J24 |
I | SubLVDS | Double | Clock, Negative |
DCLK_BP |
H24 |
I | SubLVDS | Double | Clock, Positive |
LS_CLKN |
C3 |
I | SubLVDS | Single | Clock for Low Speed Interface, Negative |
LS_CLKP |
C4 |
I | SubLVDS | Single | Clock for Low Speed Interface, Positive |
LS_WDATAN |
C5 |
I | SubLVDS | Single | Write Data for Low Speed Interface, Negative |
LS_WDATAP |
C6 |
I | SubLVDS | Single | Write Data for Low Speed Interface, Positive |
CONTROL INPUTS | |||||
DMD_DEN_ARSTZ |
E6 |
I | LPSDR | Asynchronous Reset Active Low. Logic High Enables DMD | |
LS_RDATA_A |
E19 |
O | LPSDR | Single | Read Data for Low Speed Interface |
LS_RDATA_B |
F19 |
O | LPSDR | Single | Read Data for Low Speed Interface |
TEMPERATURE SENSE DIODE | |||||
TEMP_N |
F6 |
O | Calibrated temperature diode used to assist accurate temperature measurements of DMD die | ||
TEMP_P |
G6 |
I | |||
POWER | |||||
VBIAS | A4 | Power | Supply voltage for positive bias level at micromirrors | ||
VBIAS |
A21 |
Power | |||
VOFFSET |
B3 |
Power | Supply voltage for high-voltage CMOS core logic. Supply voltage for offset level at micromirrors | ||
VOFFSET |
B4 |
Power | |||
VOFFSET |
B21 |
Power | |||
VOFFSET |
B22 |
Power | |||
VOFFSET |
J4 |
Power | |||
VOFFSET |
J21 |
Power | |||
VRESET |
B6 |
Power | Supply voltage for negative reset level at micromirrors | ||
VRESET |
B19 |
Power | |||
VDD | A5 | Power | Supply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes | ||
VDD | A20 | Power | |||
VDD |
C20 |
Power | |||
VDD |
D4 |
Power | |||
VDD |
D19 |
Power | |||
VDD |
D21 |
Power | |||
VDD |
E3 |
Power | |||
VDD |
E22 |
Power | |||
VDD |
F4 |
Power | |||
VDD |
G3 |
Power | |||
VDD |
G21 |
Power | |||
VDD |
H22 |
Power | |||
VDD |
J3 |
Power | |||
VDD |
J6 |
Power | |||
VDD |
J19 |
Power | |||
VDDI |
E5 |
Power | Supply voltage for SubLVDS receivers | ||
VDDI |
E20 |
Power | |||
VDDI |
F5 |
Power | |||
VDDI |
F20 |
Power | |||
VDDI |
G5 |
Power | |||
VDDI |
G20 |
Power | |||
VDDI |
H5 |
Power | |||
VDDI |
H20 |
Power | |||
VSS |
A1 |
Ground | Common return. Ground for all power | ||
VSS | A6 | Ground | |||
VSS | A19 | Ground | |||
VSS |
A24 |
Ground | |||
VSS | B2 | Ground | |||
VSS |
B5 |
Ground | |||
VSS | B20 | Ground | |||
VSS | B23 | Ground | |||
VSS | C19 | Ground | |||
VSS | C21 | Ground | |||
VSS | C22 | Ground | |||
VSS | D3 | Ground | |||
VSS |
D5 |
Ground | |||
VSS |
D6 |
Ground | |||
VSS |
D20 |
Ground | |||
VSS |
D22 |
Ground | |||
VSS |
E4 |
Ground | |||
VSS |
E21 |
Ground | |||
VSS |
F3 |
Ground | |||
VSS |
F21 |
Ground | |||
VSS |
F22 |
Ground | |||
VSS |
G4 |
Ground | |||
VSS |
G19 |
Ground | |||
VSS |
G22 |
Ground | |||
VSS |
H3 |
Ground | |||
VSS |
H4 |
Ground | |||
VSS |
H6 |
Ground | |||
VSS |
H19 |
Ground | |||
VSS |
H21 |
Ground | |||
VSS |
J2 |
Ground | |||
VSS |
J5 |
Ground | |||
VSS |
J20 |
Ground | |||
VSS |
J22 |
Ground | |||
VSS |
J23 |
Ground |
Pin Number | SYSTEM BOARD |
---|---|
C17 | Do not connect. |
C18 | Do not connect. |
D16 | Do not connect. Internally connected to VSS |
D17 |
Do not connect. |
D18 | Do not connect. |
E16 | Do not connect. |
E17 | Do not connect. |
E18 | Do not connect. |