DLPS229B December   2022  – August 2024 DLP4621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Third-Party Products Disclaimer
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 DMD Handling
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQX|120
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD (2) VDD = 1.95 V 220 mA
IDDI Supply current: VDDI (2) VDDI = 1.95 V 62 mA
IOFFSET Supply current: VOFFSET VOFFSET = 8.75 V 35 mA
IBIAS Supply current: VBIAS VBIAS = 16.5 V 1.5 mA
IRESET Supply current: VRESET VRESET = -10.5 V -16 mA
POWER 
PDD Supply power dissipation: VDD (2) VDD = 1.95 V 430 mW
PDDI Supply power dissipation: VDDI (2) VDDI = 1.95 V 121 mW
POFFSET Supply power dissipation: VOFFSET VOFFSET = 8.75 V 307 mW
PBIAS Supply power dissipation: VBIAS VBIAS = 16.5 V 25 mW
PRESET Supply power dissipation: VRESET VRESET = -10.5 V 168 mW
PTOTAL Supply power dissipation: Total 1045 mW
LVCMOS INPUT 
VIH High-level input voltage (3) 0.7 x VDD VDD + 0.3 V
VIL Low-level input voltage (3) -0.3 0.3 x VDD V
VIH(AC) AC input high voltage (3) 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage (3) –0.3 0.2 × VDD V
VHyst Input Hysteresis (3) See Figure 5-9 0.1 × VDD 0.4 × VDD V
IIL Low–level input current (3) VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current (3) VDD = 1.95 V; VI = 1.95 V 135 uA
LVCMOS OUTPUT 
VOH DC output high voltage (4) IOH = -2mA 0.8 × VDD V
VOL DC output low voltage (4) IOL = 2mA 0.2 × VDD V
IOZ High impedance output current VDD = 1.95V 10 µA
CAPACITANCE
CIN Input capacitance LVCMOS F = 1 MHz 10 pF
Input capacitance SubLVDS F = 1 MHz 20 pF
COUT Output capacitance F = 1 MHz 13 pF
CTEMP Temperature sense diode capacitance F = 1 MHz 20 pF
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) Supply power dissipation based on non–compressed commands and data.
(3) LPSDR input specification are for pin DMD_DEN_ARSTZ.
(4) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.