DLPS125C November   2018  – July 2023 DLP4710

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements

Device electrical characteristics are over Section 6.4 unless otherwise noted.

MIN NOM MAX UNIT
LPSDR
tr Rise slew rate(1) (30% to 80%) × VDD, Figure 6-3 1 3 V/ns
tƒ Fall slew rate(1) (70% to 20%) × VDD, Figure 6-3 1 3 V/ns
tr Rise slew rate(2) (20% to 80%) × VDD, Figure 6-3 0.25 V/ns
tƒ Fall slew rate(2) (80% to 20%) × VDD, Figure 6-3 0.25 V/ns
tc Cycle time LS_CLK, Figure 6-2 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 6-2 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 6-2 3.1 ns
tsu Setup time LS_WDATA valid before LS_CLK ↑, Figure 6-2 1.5 ns
th Hold time LS_WDATA valid after LS_CLK ↑, Figure 6-2 1.5 ns
tWINDOW Window time(1)(3) Setup time + Hold time, Figure 6-2 3.0 ns
tDERATING Window time derating(1)(3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5 0.35 ns
SubLVDS
tr Rise slew rate 20% to 80% reference points, Figure 6-4 0.7 1 V/ns
tƒ Fall slew rate 80% to 20% reference points, Figure 6-4 0.7 1 V/ns
tc Cycle time DCLK, Figure 6-6 1.79 1.85 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6-6 0.79 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6-6 0.79 ns
tsu Setup time D(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 6-6
th Hold time D(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 6-6
tWINDOW Window time Setup time + Hold time, Figure 6-6, Figure 6-7 3.0 ns
tLVDS-ENABLE+REFGEN Power-up receiver(4) 2000 ns
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3 .
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
GUID-3570A4C9-FDDE-4C9E-8FA2-A23ECF992510-low.gif
Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 6-2 LPSDR Switching Parameters
GUID-D46E7303-BCC7-441D-87E8-AD1CF4EA195B-low.gif Figure 6-3 LPSDR Input Rise and Fall Slew Rate
GUID-1532DAD3-3512-48D3-87B5-5EAA95D44C92-low.gif Figure 6-4 SubLVDS Input Rise and Fall Slew Rate
GUID-D6F047E4-706E-4D86-8F6C-8C516E3484E9-low.gif Figure 6-5 Window Time Derating Concept
GUID-A7173F0E-F2B5-44BE-B4BF-FAB76E5261BE-low.gif Figure 6-6 SubLVDS Switching Parameters
GUID-556ECFAA-4882-4749-ADBD-E7C596334DB1-low.gif
Note: Refer to Section 7.3.3 for details.
Figure 6-7 High-Speed Training Scan Window
GUID-346986D9-A479-4C1D-A055-E410C70F041F-low.gif Figure 6-8 SubLVDS Voltage Parameters
GUID-E4572C37-D484-4C6D-B9D1-5C06BF3B6AC8-low.gif Figure 6-9 SubLVDS Waveform Parameters
GUID-71E8ADDB-3780-46E4-8314-A6972440C00F-low.gif Figure 6-10 SubLVDS Equivalent Input Circuit
GUID-1833CD8F-1F35-4164-BBC6-6CD184FD8E2D-low.gif Figure 6-11 LPSDR Input Hysteresis
GUID-F39C2C9C-CE98-4074-8D58-23EF3F37661E-low.gif Figure 6-12 LPSDR Read Out
GUID-1CA84CE2-EB18-470B-8D39-19E77382D38B-low.gif
See Timing for more information.
Figure 6-13 Test Load Circuit for Output Propagation Measurement