DLPS178C may   2020  – july 2023 DLP4710LC

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1.      46
      2. 8.2.1 Design Requirements
      3. 8.2.2 Detailed Design Procedure
      4. 8.2.3 Application Curve
  10. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Requirements

A high-accuracy, 3D depth capture product is created by using a DLP chipset comprised of DLP4710LC DMD, 2xDLPC3479 controller and DLPA3000 PMIC/LED drive. The DLPC3479 simplifies the pattern generation, the DLPA3000 provides the needed analog functions and DMD displays the required patterns for accurate 3D depth capture. In addition to the three DLP devices in the chipset, other components may be required to complete the application. Minimally, a flash component is required to store patterns, the software, and the firmware in order to control the DLPC3479 controller. DLPC3479 controller supports any illumination source including IR light source (LEDs or VCSEL), UV light source or visible light source (Red, Green or Blue LEDs or lasers).

To send commands from the host processor to the DLPC3479, connect the two via I2C. The only power supplies needed for the DLP4710LC chipset is the input power (SYSPWR). All other needed supplies are being provided by the DLPA3000 or DLPA3005 PMIC for this chipset. A single signal (PROJ_ON) controls the entire DLP system power. When PROJ_ON is high, the DLP system turns on and when PROJ_ON is low, the DLPC3479 turns off and draws only a few microamperes of current on SYSPWR.

The TSTPT_2 pin on the master controller outputs a 25ns pulse width that should be connected to the 3DR (input) pin of the slave controller. In case VCC_INTF is not set to 1.8V, a voltage translator is required. The propagation delay between the rising edge of TSTPT_2 pin on the master controller and the VIH of 3DR (input) pin on slave controller is recommended to be under 10ns.