DLPS273A May   2024  – December 2024 DLP472TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS
tr Rise time(1) 20% to 80% reference points 25 ns
tf Fall time(1) 80% to 20% reference points 25 ns
LOW SPEED INTERFACE (LSIF)
tr Rise time(2) 20% to 80% reference points 450 ps
tf Fall time(2) 80% to 20% reference points 450 ps
tW(H) Pulse duration high(3) LS_CLK. 50% to 50% reference points 3.1 ns
tW(L) Pulse duration low(3) LS_CLK. 50% to 50% reference points 3.1 ns
tsu Setup time(4) LS_WDATA valid before rising edge of LS_CLK (differential) 1.5 ns
th Hold time(4) LS_WDATA valid after rising edge of LS_CLK (differential) 1.5 ns
HIGH SPEED SERIAL INTERFACE (HSSI)
tr Rise time(5)(6)—data from -A1 to A1 minimum eye height specification 50 115 ps
Rise time(5)(6)—clock from -A1 to A1 minimum eye height specification 50 135 ps
tf Fall time(5)(6)—data from A1 to -A1 minimum eye height specification 50 115 ps
Fall time(5)(6)—clock from A1 to -A1 minimum eye height specification 50 135
tW(H) Pulse duration high(7) DCLK. 50% to 50% reference points 0.275 ns
tW(L) Pulse duration low(7) DCLK. 50% to 50% reference points 0.275 ns
(1) See Figure 5-10 for rise time and fall time for LVCMOS.
(2) See Figure 5-6 for rise time and fall time for LSIF.
(3) See Figure 5-5 for pulse duration high and low time for LSIF.
(4) See Figure 5-5 for setup and hold time for LSIF.
(5) See Figure 5-12 for rise time and fall time for HSSI Eye Characteristics.
(6) See Figure 5-11 for rise time and fall time for HSSI.
(7) See Figure 5-13 for pulse duration high and low for HSSI.
DLP472TE LSIF Waveform Requirements Figure 5-4 LSIF Waveform Requirements
Equation 1. DLP472TE
Equation 2. DLP472TE
DLP472TE LSIF Timing Requirements Figure 5-5 LSIF Timing Requirements
DLP472TE LSIF Rise, Fall Time Slew Figure 5-6 LSIF Rise, Fall Time Slew
DLP472TE LSIF Voltage Requirements Figure 5-7 LSIF Voltage Requirements
DLP472TE LSIF Equivalent Input Figure 5-8 LSIF Equivalent Input
DLP472TE LVCMOS Input Hysteresis Figure 5-9 LVCMOS Input Hysteresis
DLP472TE LVCMOS Rise, Fall Time Slew Rate Figure 5-10 LVCMOS Rise, Fall Time Slew Rate
DLP472TE HSSI Waveform Requirements
A. See Equation 1 and Equation 2.
Figure 5-11 HSSI Waveform Requirements
Equation 3. DLP472TE
Equation 4. DLP472TE
DLP472TE HSSI Eye Characteristics Figure 5-12 HSSI Eye Characteristics
DLP472TE HSSI CLK Characteristics Figure 5-13 HSSI CLK Characteristics