DLPS273A May   2024  – December 2024 DLP472TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DLP472TE FYW Package149-Pin PGABottom ViewFigure 4-1 FYW Package149-Pin PGABottom View
CAUTION:

Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable, long-term operation of the 0.47” 4K UHD S453 DMD. Refer to the PCB Design Requirements for TI DLP Digital Micromirror Devices application report for specific details and guidelines before designing the board.

Table 4-1 Pin Functions
PININPUT-OUTPUT(1)DESCRIPTIONTRACE LENGTH (mm)
NAMENo.
D_AP(0) J1 I High-speed differential data pair lane A0 16.316
D_AN(0) H1 I High-speed differential data pair lane A0 16.316
D_AP(1) G1 I High-speed differential data pair lane A1 16.469
D_AN(1) F1 I High-speed differential data pair lane A1 16.468
D_AP(2) F2 I High-speed differential data pair lane A2 15.661
D_AN(2) E2 I High-speed differential data pair lane A2 15.661
D_AP(3) D2 I High-speed differential data pair lane A3 15.053
D_AN(3) C2 I High-speed differential data pair lane A3 15.054
D_AP(4) A3 I High-speed differential data pair lane A4 12.948
D_AN(4) A4 I High-speed differential data pair lane A4 12.948
D_AP(5) A5 I High-speed differential data pair lane A5 10.644
D_AN(5) A6 I High-speed differential data pair lane A5 10.644
D_AP(6) A7 I High-speed differential data pair lane A6 8.558
D_AN(6) A8 I High-speed differential data pair lane A6 8.557
D_AP(7) A9 I High-speeddifferential data pair lane A7 6.688
D_AN(7) A10 I High-speed differential data pair lane A7 6.688
DCLK_AP C1 I High-speed differential clock A 17.975
DCLK_AN D1 I High-speed differential clock A 17.795
D_BP(0) A11 I High-speed differential data pair lane B0 4.592
D_BN(0) A12 I High-speed differential data pair lane B0 4.591
D_BP(1) A13 I High-speed differential data pair lane B1 6.440
D_BN(1) A14 I High-speed differential data pair lane B1 6.440
D_BP(2) A15 I High-speed differential data pair lane B2 8.838
D_BN(2) A16 I High-speed differential data pair lane B2 8.838
D_BP(3) A18 I High-speed differential data pair lane B3 12.117
D_BN(3) A19 I High-speed differential data pair lane B3 12.118
D_BP(4) D19 I High-speed differential data pair lane B4 11.078
D_BN(4) C19 I High-speed differential data pair lane B4 11.078
D_BP(5) H20 I High-speed differential data pair lane B5 14.504
D_BN(5) J20 I High-speed differential data pair lane B5 14.504
D_BP(6) D20 I High-speed differential data pair lane B6 11.647
D_BN(6) E20 I High-speed differential data pair lane B6 11.646
D_BP(7) F20 I High-speed differential data pair lane B7 12.305
D_BN(7) G20 I High-speed differential data pair lane B7 12.305
DCLK_BP B17 I High-speed differential clock B 10.064
DCLK_BN B18 I High-speed differential clock B 10.243
LS_WDATA_P T10 I LVDS data 8.752
LS_WDATA_N R11 I LVDS data 1.475
LS_CLK_P R9 I LVDS CLK 8.656
LS_CLK_N R10 I LVDS CLK 7.805
LS_RDATA_A_BISTA T13 O LVCMOS output 2.804
BIST_B T12 O LVCMOS output 3.075
AMUX_OUT B20 O Analog test mux 10.712
DMUX_OUT R14 O Digital test mux 2.997
DMD_DEN_ARSTZ T11 I ARSTZ 2.982
TEMP_N R8 I Temp diode N 9.806
TEMP_P R7 I Temp diode P 11.986
VDDB13, B7, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18PDigital Core supply voltagePlane
VDDAB11, B16, B4, B9, C20, D3, E18, G2, G19PHSSI supply voltagePlane
VRESETB3, R1PSupply voltage for negative bias of micromirror reset signalPlane
VBIASE1, P1PSupply voltage for positive bias of micromirror reset signalPlane
VOFFSETA20, B2, T1, T20PSupply voltage for HVCMOS logic,stepped up logic levelPlane
VSSA17, B10, B14, B6, D18, F3, F19, J3, K19, K2, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19GGroundPlane
VSSAB12, B15, B19, B5, B8, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9GGroundPlane
N/CF18, G18, H18, J18, J19, K18, K20, L18, L20, M18, M19, M20, R15, R16, T14, T15No connect
(1) I=Input, O=Output, P=Power, G=Ground, NC = No Connect