DLPS273A May   2024  – December 2024 DLP472TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MINMAXUNIT
SUPPLY VOLTAGE
VDDSupply voltage for LVCMOS core logic and LVCMOS low-speed interface (LSIF)(1)–0.52.3V
VDDA Supply voltage for high-speed serial interface (HSSI) receivers(1)–0.32.2V
VOFFSETSupply voltage for HVCMOS and micromirror electrode(1)(2)–0.511V
VBIASSupply voltage for micromirror electrode(1)–0.519V
VRESETSupply voltage for micromirror electrode(1)–150.5V
| VDDA – VDD |Supply voltage delta (absolute value)(3)0.3V
| VBIAS – VOFFSET |Supply voltage delta (absolute value)(4)11V
| VBIAS – VRESET |Supply voltage delta (absolute value)(5)34V
INPUT VOLTAGE
Input voltage for other inputs – LSIF and LVCMOS(1)–0.52.46V
Input voltage for other inputs – HSSI(1)(6)–0.2VDDAV
LOW SPEED INTERFACE (LSIF)
fCLOCKLSIF clock frequency (LS_CLK)130MHz
| VID |LSIF differential input voltage magnitude(6)810mV
IID LSIF differential input current10mA
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCKHSSI clock frequency (DCLK)1.65GHz
| VID |HSSI differential input voltage magnitude Data Lane(6)700mV
| VID |HSSI differential input voltage magnitude Clock Lane(6)700mV
ENVIRONMENTAL
TARRAYTemperature, operating(7)090°C
Temperature, non-operating(7)–4090°C
TDPDew point temperature, operating and non–operating (noncondensing)81°C
(1) All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in the Micromirror Array Temperature Calculation section.