DLPS273 Data sheet

DLPS273 May 2024 DLP472TE

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5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.

		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGES ⁽¹⁾ ⁽²⁾
V_DD	Supply voltage for LVCMOS core logic and low-speed interface (LSIF)	1.71	1.8	1.95	V
V_DDA	Supply voltage for high speed serial interface (HSSI) receivers	1.71	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽³⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for micromirror electrode	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode	–14.5	–14	–13.5	V
\| V_DDA – V_DD \|	Supply voltage delta, absolute value⁽⁴⁾			0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta, absolute value⁽⁵⁾			10.5	V
\| V_BIAS – V_RESET \|	Supply voltage delta, absolute value			33	V
LVCMOS INPUT
V_IH	High-level input voltage⁽⁶⁾	0.7 × V_DD			V
V_IL	Low-level input voltage⁽⁶⁾			0.3 x V_DD	V
LOW SPEED SERIAL INTERFACE (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)⁽⁸⁾	108	120	130	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
\| V_ID \|	LSIF differential input voltage magnitude⁽⁸⁾	150	350	440	mV
V_LVDS	LSIF voltage⁽⁸⁾	575		1520	mV
V_CM	Common mode voltage⁽⁸⁾	700	900	1300	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance	80	100	120	Ω
HIGH SPEED SERIAL INTERFACE (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)⁽⁷⁾	1.2		1.6	GHz
DCD_IN	HSSI duty cycle distortion (DCLK)	44%	50%	56%
\| V_ID \| Data	HSSI differential input voltage magnitude Data Lane⁽⁷⁾	100		600	mV
\| V_ID \| CLK	HSSI differential input voltage magnitude Clock Lane⁽⁷⁾	295		600	mV
VCM_DCData	Input common mode voltage (DC) Data Lane⁽⁷⁾	200	600	800	mV
VCM_DC CLK	Input common mode voltage (DC) Clk Lane⁽⁷⁾	200	600	800	mV
VCM_ACp-p	AC peak to peak (ripple) on common mode voltage of Data Lane and Clock Lane⁽⁷⁾			100	mV
Z_LINE	Line differential impedance (PWB/trace)		100		Ω
Z_IN	Internal differential termination resistance ( R_Xterm )	80	100	120	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long–term operational⁽⁹⁾⁽¹⁰⁾⁽¹¹⁾	10		40 to 70 ⁽¹²⁾	°C
T_ARRAY	Array temperature, short-term operational, 500 hr max⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_DP-AVG	Average dew point temperature (non–condensing)⁽¹⁴⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁵⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	months
Q_AP-LL	Window Aperture illumination overfill⁽¹⁶⁾⁽¹⁷⁾⁽¹⁸⁾			17	W/cm²
LAMP ILLUMINATION
ILL_UV	Illumination power at wavelength < 395nm⁽⁹⁾⁽²⁰⁾		0.68	2	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥395nm and ≤800nm⁽¹⁹⁾⁽²⁰⁾			36.8	W/cm²
ILL_IR	Illumination power at wavelength > 800nm⁽²⁰⁾			10	mW/cm²
SOLID STATE ILLUMINATION
ILL_UV	Illumination power at wavelength < 410nm⁽⁹⁾⁽²⁰⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths between ≥410nm and ≤800nm⁽¹⁹⁾⁽²⁰⁾			46.8	W/cm2
ILL_IR	Illumination power at wavelength > 800nm⁽²⁰⁾			10	mW/cm²
ILL_BLU	Illumination power at wavelengths between ≥410nm and ≤475nm⁽¹⁹⁾⁽²⁰⁾			14.9	W/cm2
ILL_BLU1	Illumination power at wavelengths between ≥410nm and ≤440nm⁽¹⁹⁾⁽²⁰⁾			2.4	W/cm2

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are regarding the V_SS ground pins.

(3) V_OFFSETsupply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than the specified limit.

(5) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than the specified limit.

(6) LVCMOS input pin is DMD_DEN_ARSTZ.

(8) See the high-speed serial interface (HSSI) timing requirements in Timing Requirements.

(9) See the low-speed interface (LSIF) timing requirements in Timing Requirements.

(20) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces the device's lifetime.

(21) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in Figure 6-1 using Section 6.6.

(22) Long-term is defined as the usable life of the device.

(23) Per Figure 5-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 6.9 for a definition of a micromirror landed duty cycle

(24) Short-term is the total cumulative time over the useful life of the device.

(25) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(26) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of CTELR.

(27) Applies to region defined in Figure 5-2.

(28) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may cause system performance degradation.

(29) To calculate, see Section 6.8.

(30) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).

(31) To calculate, see Section 6.6.