DLPS247 August   2024 DLP472TP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     12
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     17
    11. 5.9  System Mounting Interface Loads
    12.     19
    13. 5.10 Micromirror Array Physical Characteristics
    14.     21
    15. 5.11 Micromirror Array Optical Characteristics
    16.     23
    17. 5.12 Window Characteristics
    18. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
MIN TYP MAX UNIT
SUPPLY VOLTAGE RANGE
VDD Supply voltage for LVCMOS core logic(1)(2)
Supply voltage for LPSDR low-speed interface(1)(2)
1.71 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers(1)(2) 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(1)(2)(3) 9.5 10 10.5 V
VBIAS Supply voltage for mirror electrode(1)(2) 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode(1)(2) –14.5 –14 –13.5 V
|VDDI- VDD| Supply voltage delta (absolute value)(1)(2)(4) 0.3 V
|VBIAS-VOFFSET| Supply voltage delta (absolute value)(1)(2)(5) 10.5 V
|VBIAS- VRESET| Supply voltage delta (absolute value)(1)(2)(6) 33 V
CLOCK FREQUENCY
fclock Clock frequency for low speed interface LS_CLK(7) 108 120 MHz
Clock frequency for high-speed interface DCLK (8) 720 MHz
DCDIN Duty cycle distortion 44 56 %
SUBLVDS INTERFACE
|VID| LVDS differential input voltage magnitude(8) 150 250 350 mV
VCM Common mode voltage(8) 700 900 1100 mV
VSUBLVDS SubLVDS voltage(8) 525 1275 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance(10) 80 100 120 Ω
100Ω differential PCB trace 6.35 152.4 mm
ENVIRONMENTAL
TARRAY Array temperature, long-term operation(9)(10)(11)(12) 10 40 to 70 °C
Array temperature, short-term operation, 500 hr max(10)(13) 0 10 °C
TWindow Window temperature, operational(14) 85 °C
|TDELTA| Absolute Temperature difference between any point on the window edge and the ceramic test point TP1(16) 15 °C
TDP-AVG Average dew point temperature, (non-condensing)(15) 24 °C
TDP-ELR Elevated dew point temperature range, (non-condensing)(16) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 6 Months
ILLUMINATION
ILLUV Illumination, wavelength < 410nm(9) 10 mW/cm2
ILLVIS Illumination power at wavelengths ≥ 410nm and ≤ 800nm(17) 20.5 W/cm2
ILLIR Illumination, wavelength between > 800nm 10 mW/cm2
ILLBLU Illumination power at wavelengths ≥ 410nm and ≤ 475nm(17) 6.5 W/cm2
ILLBLU1 Illumination power at wavelengths ≥ 410nm and ≤ 445nm(17) 1.2 W/cm2
ILLθ Illumination marginal ray angle(18) 55 deg
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are required to operate the DMD.
All voltage values are with respect to the VSS ground pins.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
Refer to the SubLVDS timing requirements in Section 5.8.
Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) and the package thermal resistance using the Micromirror Array Temperature Calculation.
Per Maximum Recommended Array Temperature—Derating Curve, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
Long-term is defined as the usable life of the device.
Short-term is the total cumulative time over the useful life of the device.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge. The window test points TP2, TP3, TP4, and TP5 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).
The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.