DLPS247 August   2024 DLP472TP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     12
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     17
    11. 5.9  System Mounting Interface Loads
    12.     19
    13. 5.10 Micromirror Array Physical Characteristics
    14.     21
    15. 5.11 Micromirror Array Optical Characteristics
    16.     23
    17. 5.12 Window Characteristics
    18. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PIN(2) TYPE(1) DESCRIPTION TERMINATION TRACE LENGTH (mm)
NAME PAD ID
D_AP(0) A2 I High-speed Differential Data Pair lane A0 Differential 100Ω 3.75497
D_AN(0) B2 I High-speed Differential Data Pair lane A0 Differential 100Ω 3.75482
D_AP(1) A6 I High-speed Differential Data Pair lane A1 Differential 100Ω 4.62509
D_AN(1) B6 I High-speed Differential Data Pair lane A1 Differential 100Ω 4.625
D_AP(2) C1 I High-speed Differential Data Pair lane A2 Differential 100Ω 3.59503
D_AN(2) C2 I High-speed Differential Data Pair lane A2 Differential 100Ω 3.59513
D_AP(3) C6 I High-speed Differential Data Pair lane A3 Differential 100Ω 5.12758
D_AN(3) C7 I High-speed Differential Data Pair lane A3 Differential 100Ω 5.12745
D_AP(4) G3 I High-speed Differential Data Pair lane A4 Differential 100Ω 1.60057
D_AN(4) G4 I High-speed Differential Data Pair lane A4 Differential 100Ω 1.6004
D_AP(5) F7 I High-speed Differential Data Pair lane A5 Differential 100Ω 3.64067
D_AN(5) F6 I High-speed Differential Data Pair lane A5 Differential 100Ω 3.64091
D_AP(6) F4 I High-speed Differential Data Pair lane A6 Differential 100Ω 1.58206
D_AN(6) F5 I High-speed Differential Data Pair lane A6 Differential 100Ω 1.58187
D_AP(7) H6 I High-speed Differential Data Pair lane A7 Differential 100Ω 2.70067
D_AN(7) G6 I High-speed Differential Data Pair lane A7 Differential 100Ω 2.70086
DCLK_AP E5 I High-speed Differential Clock A Differential 100Ω 2.96493
DCLK_AN D5 I High-speed Differential Clock A Differential 100Ω 2.9653
D_BP(0) B30 I High-speed Differential Data Pair lane B0 Differential 100Ω 3.57087
D_BN(0) A30 I High-speed Differential Data Pair lane B0 Differential 100Ω 3.57064
D_BP(1) C32 I High-speed Differential Data Pair lane B1 Differential 100Ω 4.2546
D_BN(1) B32 I High-speed Differential Data Pair lane B1 Differential 100Ω 4.25425
D_BP(2) A28 I High-speed Differential Data Pair lane B2 Differential 100Ω 4.97968
D_BN(2) B28 I High-speed Differential Data Pair lane B2 Differential 100Ω 4.97953
D_BP(3) C31 I High-speed Differential Data Pair lane B3 Differential 100Ω 3.12736
D_BN(3) C30 I High-speed Differential Data Pair lane B3 Differential 100Ω 3.12743
D_BP(4) C27 I High-speed Differential Data Pair lane B4 Differential 100Ω 5.44353
D_BN(4) B27 I High-speed Differential Data Pair lane B4 Differential 100Ω 5.4433
D_BP(5) D28 I High-speed Differential Data Pair lane B5 Differential 100Ω 3.32124
D_BN(5) D27 I High-speed Differential Data Pair lane B5 Differential 100Ω 3.32115
D_BP(6) F30 I High-speed Differential Data Pair lane B6 Differential 100Ω 2.99334
D_BN(6) E30 I High-speed Differential Data Pair lane B6 Differential 100Ω 2.99374
D_BP(7) G27 I High-speed Differential Data Pair lane B7 Differential 100Ω 3.14865
D_BN(7) G28 I High-speed Differential Data Pair lane B7 Differential 100Ω 3.14902
DCLK_BP D29 I High-speed Differential Clock B Differential 100Ω 5.03976
DCLK_BN D30 I High-speed Differential Clock B Differential 100Ω 5.0395
D_CP(0) J4 I High-speed Differential Data Pair lane C0 Differential 100Ω 2.06577
D_CN(0) H4 I High-speed Differential Data Pair lane C0 Differential 100Ω 2.06568
D_CP(1) J7 I High-speed Differential Data Pair lane C1 Differential 100Ω 4.87119
D_CN(1) J6 I High-speed Differential Data Pair lane C1 Differential 100Ω 4.87131
D_CP(2) K5 I High-speed Differential Data Pair lane C2 Differential 100Ω 4.69951
D_CN(2) J5 I High-speed Differential Data Pair lane C2 Differential 100Ω 4.69926
D_CP(3) L4 I High-speed Differential Data Pair lane C3 Differential 100Ω 3.27735
D_CN(3) L5 I High-speed Differential Data Pair lane C3 Differential 100Ω 3.27722
D_CP(4) L2 I High-speed Differential Data Pair lane C4 Differential 100Ω 4.65167
D_CN(4) M2 I High-speed Differential Data Pair lane C4 Differential 100Ω 4.6513
D_CP(5) M3 I High-speed Differential Data Pair lane C5 Differential 100Ω 5.70359
D_CN(5) N3 I High-speed Differential Data Pair lane C5 Differential 100Ω 5.70352
D_CP(6) M5 I High-speed Differential Data Pair lane C6 Differential 100Ω 2.57704
D_CN(6) M6 I High-speed Differential Data Pair lane C6 Differential 100Ω 2.57727
D_CP(7) N7 I High-speed Differential Data Pair lane C7 Differential 100Ω 3.77278
D_CN(7) M7 I High-speed Differential Data Pair lane C7 Differential 100Ω 3.77317
DCLK_CP K2 I High-speed Differential Clock C Differential 100Ω 2.3747
DCLK_CN J2 I High-speed Differential Clock C Differential 100Ω 2.37429
D_DP(0) G29 I High-speed Differential Data Pair lane D0 Differential 100Ω 3.67925
D_DN(0) F29 I High-speed Differential Data Pair lane D0 Differential 100Ω 3.6794
D_DP(1) F27 I High-speed Differential Data Pair lane D1 Differential 100Ω 4.73751
D_DN(1) E27 I High-speed Differential Data Pair lane D1 Differential 100Ω 4.73796
D_DP(2) K30 I High-speed Differential Data Pair lane D2 Differential 100Ω 2.76933
D_DN(2) K29 I High-speed Differential Data Pair lane D2 Differential 100Ω 2.76936
D_DP(3) J27 I High-speed Differential Data Pair lane D3 Differential 100Ω 3.07794
D_DN(3) K27 I High-speed Differential Data Pair lane D3 Differential 100Ω 3.07804
D_DP(4) M30 I High-speed Differential Data Pair lane D4 Differential 100Ω 3.60026
D_DN(4) L30 I High-speed Differential Data Pair lane D4 Differential 100Ω 3.60028
D_DP(5) M27 I High-speed Differential Data Pair lane D5 Differential 100Ω 3.24012
D_DN(5) L27 I High-speed Differential Data Pair lane D5 Differential 100Ω 3.24002
D_DP(6) N26 I High-speed Differential Data Pair lane D6 Differential 100Ω 4.69564
D_DN(6) M26 I High-speed Differential Data Pair lane D6 Differential 100Ω 4.69594
D_DP(7) M31 I High-speed Differential Data Pair lane D7 Differential 100Ω 3.97347
D_DN(7) M32 I High-speed Differential Data Pair lane D7 Differential 100Ω 3.97352
DCLK_DP H29 I High-speed Differential Clock D Differential 100Ω 1.7593
DCLK_DN J29 I High-speed Differential Clock D Differential 100Ω 1.75933
LS_WDATA D4 I LVDS Data 2.29224
LS_CLK C4 I LVDS CLK 1.73951
LS_RDATA_A C5 O LVCMOS Output 2.72344
LS_RDATA_B D3 O LVCMOS Output 2.22814
LS_RDATA_C E3 O LVCMOS Output 3.22863
LS_RDATA_D F3 O LVCMOS Output 4.90151
DMD_DEN_ARSTZ D2 I ARSTZ 1.80911
TEMP_N N1 I Temp Diode N 1.84006
TEMP_P M1 I Temp Diode P 2.62822
VDD A3, A4, C26, D1, D6, D7, D26, E2, E6, E7, E26, F2, G30, H28, H30, J26, J30, K1, K6, K26, K31, K32, L1, L31, L32, N2 P Digital Core Supply Voltage 14.26561
VDDI A5, B5, F26, G26, H26, H27, K7, L7 P SubLVDS supply voltage 3.72532
VRESET B3, B26 P Supply voltage for negative bias of micromirror reset signal 25.57603
VBIAS A27, B4 P Supply voltage for positive bias of micromirror reset signal 24.70004
VOFFSET A26, C3, L6, L26 P Supply voltage for HVCMOS logic, stepped up logic level 8.73417
VSS A1, A7, A29, A31, A32, B1, B7, B29, B31, C28, C29, D31, D32, E4, E28, E29, F28, G5, G7, H2, H3, H5, H7, J3, J28, K3, K4, K28, L3, L28, L29, M4, M28, M29, N4, N5, N6, N27, N31, N32 G Ground 24.6246
N/C N28, N29, N30, L25, K25, J25, H25, G25, F25, E25, D25 NC No Connect Pin None
I=Input, O=Output, P=Power, G=Ground, NC=No Connect
Only 163 pins are electrically connected for functional use