DLPS013H April 2010 – December 2024 DLP5500
PRODUCTION DATA
Signals should be routed to have a matched impedance of 50Ω ±10% except for LVDS differential pairs (DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn) and DDR2 differential clock pairs (MEM_CLK_nn), which should be matched to 100Ω ±10% across each pair.