DLPS013 Data sheet

DLPS013H April 2010 – December 2024 DLP5500

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FYA|149
- MCLG018B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SUPPLY VOLTAGES⁽¹⁾ ⁽²⁾
V_CC	Supply voltage for LVCMOS core logic	3.15	3.3	3.45	V
V_CCI	Supply voltage for LVDS receivers	3.15	3.3	3.45	V
V_CC2	Mirror electrode and HVCMOS supply voltage ⁽¹⁾⁽²⁾	8.25	8.5	8.75	V
\|V_CCI–V_CC\|	Supply voltage delta (absolute value) ⁽³⁾			0.3	V
V_MBRST	Micromirror clocking pulse voltages	-27		26.5	V
LVCMOS PINS
V_IH	High level Input voltage ⁽⁴⁾	1.7	2.5	VCC + 0.15	V
V_IL	Low level Input voltage⁽⁴⁾	– 0.3		0.7	V
I_OH	High level output current at V_OH = 2.4 V			–20	mA
I_OL	Low level output current at V_OL = 0.4 V			15	mA
T_PWRDNZ	PWRDNZ pulse width⁽⁵⁾	10			ns
SCP INTERFACE
ƒ_clock	SCP clock frequency⁽⁶⁾			500	kHz
t_{SCP_SKEW}	Time between valid SCPDI and rising edge of SCPCLK⁽⁷⁾	–800		800	ns
t_{SCP_DELAY}	Time between valid SCPDO and rising edge of SCPCLK⁽⁷⁾			700	ns
t_{SCP_BYTE_INTERVAL}	Time between consecutive bytes	1			µs
t_{SCP_NEG_ENZ}	Time between falling edge of SCPENZ and the first rising edge of SCPCLK	30			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			µs
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tri-state)			1.5	ns
ƒ_clock	SCP circuit clock oscillator frequency ⁽⁸⁾	9.6		11.1	MHz
LVDS INTERFACE
ƒ_clock	Clock frequency for LVDS interface, DCLK (all channels)		200		MHz
\|V_ID\|	Input differential voltage (absolute value)⁽⁹⁾	100	400	600	mV
V_CM	Common mode ⁽⁹⁾		1200		mV
V_LVDS	LVDS voltage⁽⁹⁾	0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL ⁽¹⁰⁾
T_DMD	Long-term DMD temperature (operational) ⁽¹¹⁾ ⁽¹²⁾ ⁽¹⁶⁾	10		40 to 70⁽¹²⁾	°C
T_DMD	Short-term DMD temperature (operational)⁽¹¹⁾ ⁽¹⁷⁾	–20		75	°C
T_WINDOW	Window temperature – operational⁽¹³⁾			90	°C
T_{CERAMIC-WINDOW-DELTA}	Delta ceramic-to-window temperature -operational ⁽¹³⁾ ⁽¹⁴⁾			30	°C
	Long-term dew point (operational & non-operational)			24	°C
	Short-term dew point⁽¹⁶⁾ ⁽¹⁸⁾ (operational & non-operational)			28	°C
ILL_UV	Illumination, wavelength < 420 nm			0.68	mW/cm²
ILL_VIS	Illumination, wavelengths between 420 and 700 nm			Thermally Limited⁽¹⁵⁾	mW/cm²
ILL_IR	Illumination, wavelength > 700 nm			10	mW/cm²

(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit.

(4) Tester Conditions for V_IH and V_IL:
Frequency = 60MHz. Maximum Rise Time = 2.5ns at (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5ns at (80% to 20%)

(5) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.

(6) The SCP clock is a gated clock. The duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(7) Refer to Figure 6-3.

(8) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

(9) Refer to Figure 6-5, Figure 6-6, and Figure 6-7.

(10) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(11) DMD Temperature is the worst-case of any thermal test point in Figure 7-4, or the active array as calculated by the Section 7.6.3.

(12) Per Figure 6-1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.

(13) Window temperature as measured at thermal test points TP2, TP3, TP4, and TP5 in Figure 7-4.The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-4 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.

(14) Ceramic package temperature as measured at test point 1 (TP 1) in Figure 7-4.

(15) Refer to Section 6.5 and Section 7.6.

(16) Long-term is defined as the average over the usable life of the device.

(17) Short-term is defined as less than 60 cumulative days over the usable life of the device.

(18) Dew points beyond the specified long-term dew point (operating, non-operating, or storage) are for short-term conditions only, where short-term is defined as< 60 cumulative days over the usable life of the device.

DLP5500 Max Recommended DMD Temperature—Derating Curve

Figure 6-1 Max Recommended DMD Temperature—Derating Curve