DLPS101B November   2017  – February 2023 DLP550JE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Power Interface
      2. 7.2.2 Timing
    3. 7.3 Optical Interface and System Image Quality Considerations
      1. 7.3.1 Numerical Aperture and Stray Light Control
      2. 7.3.2 Pupil Match
      3. 7.3.3 Illumination Overfill
    4. 7.4 Micromirror Array Temperature Calculation
      1. 7.4.1 Micromirror Array Temperature Calculation
    5. 7.5 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.5.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.5.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.5.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.5.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power-Up and Power-Down Procedures
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 Support Resources
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).#T4989946-2
MIN MAX UNIT
SUPPLY VOLTAGES
VCC Supply voltage for LVCMOS core logic#T4989946-31 –0.5 4 V
VCCI Supply voltage for LVDS Interface#T4989946-31 –0.5 4 V
VOFFSET Micromirror Electrode and HVCMOS voltage#T4989946-31#T4989946-33 –0.5 9 V
VMBRST Voltage applied to MBRST[0:15] Input Pins –28 28 V
|VCC – VCCI| Supply voltage change#DLPS101933 0.3 V
INPUT VOLTAGES
Input voltage for all other input pins#T4989946-31 –0.5 VCC + 0.3 V
|VID| Input differential voltage (absolute value) #T4989946-32 700 mV
CLOCKS
ƒclock Clock frequency for LVDS interface, DCLK_A 400 MHz
ƒclock Clock frequency for LVDS interface, DCLK_B 400 MHz
ENVIRONMENTAL
TARRAY and TWINDOW Temperature, operating#DLPS1015831 0 90 °C
Temperature, non-operating #DLPS1015831 –40 90 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1#DLPS1011043 30 °C
TDP Dew Point Temperature, operating and non-operating (non-condensing) 81 °C
(1) All voltages are referenced to common ground VSS. Voltages VCC, VCCI, and VOFFSET are required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw.
(4) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(5) The highest temperature of the active array (as calculated by the GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC) or of any point along the Window Edge as defined in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The locations of thermal test points TP2, TP3, TP4, and TP5 in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.
(6) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The window test points TP2, TP3, TP4, and TP5 shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(7) Stresses beyond those listed under #GUID-6267F3F2-F83A-40EA-9D2B-C2D526C613BF may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.html#GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.