DLPS101B November   2017  – February 2023 DLP550JE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Power Interface
      2. 7.2.2 Timing
    3. 7.3 Optical Interface and System Image Quality Considerations
      1. 7.3.1 Numerical Aperture and Stray Light Control
      2. 7.3.2 Pupil Match
      3. 7.3.3 Illumination Overfill
    4. 7.4 Micromirror Array Temperature Calculation
      1. 7.4.1 Micromirror Array Temperature Calculation
    5. 7.5 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.5.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.5.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.5.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.5.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power-Up and Power-Down Procedures
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 Support Resources
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-8E6682CE-1D52-407E-B65B-9E59359F801F-low.gifFigure 5-1 FYA Package149-Pin Bottom View
Table 5-1 Pin Functions
PIN(1) TYPE
(I/O/P )		 SIGNAL DATA
RATE(2)		 INTERNAL
TERM(3)		 CLOCK DESCRIPTION TRACE
(mils)(4)
NAME NO.
DATA INPUTS
D_AN1 G20 Input LVCMOS DDR Differential DCLK_A Input data bus A (LVDS) 760.78
D_AP1 H20 Input LVCMOS DDR Differential DCLK_A 760.86
D_AN3 H19 Input LVCMOS DDR Differential DCLK_A 760.73
D_AP3 G19 Input LVCMOS DDR Differential DCLK_A 760.76
D_AN5 F18 Input LVCMOS DDR Differential DCLK_A 760.73
D_AP5 G18 Input LVCMOS DDR Differential DCLK_A 760.81
D_AN7 E18 Input LVCMOS DDR Differential DCLK_A 760.77
D_AP7 D18 Input LVCMOS DDR Differential DCLK_A 760.81
D_AN9 C20 Input LVCMOS DDR Differential DCLK_A 760.67
D_AP9 D20 Input LVCMOS DDR Differential DCLK_A 760.74
D_AN11 B18 Input LVCMOS DDR Differential DCLK_A 760.68
D_AP11 A18 Input LVCMOS DDR Differential DCLK_A 760.77
D_AN13 A20 Input LVCMOS DDR Differential DCLK_A 760.82
D_AP13 B20 Input LVCMOS DDR Differential DCLK_A 760.77
D_AN15 B19 Input LVCMOS DDR Differential DCLK_A 760.79
D_AP15 A19 Input LVCMOS DDR Differential DCLK_A 760.75
D_BN1 K20 Input LVCMOS DDR Differential DCLK_B Input data bus B (LVDS) 760.72
D_BP1 J20 Input LVCMOS DDR Differential DCLK_B 760.80
D_BN3 J19 Input LVCMOS DDR Differential DCLK_B 760.79
D_BP3 K19 Input LVCMOS DDR Differential DCLK_B 760.82
D_BN5 L18 Input LVCMOS DDR Differential DCLK_B 760.77
D_BP5 K18 Input LVCMOS DDR Differential DCLK_B 760.85
D_BN7 M18 Input LVCMOS DDR Differential DCLK_B 760.78
D_BP7 N18 Input LVCMOS DDR Differential DCLK_B 760.81
D_BN9 P20 Input LVCMOS DDR Differential DCLK_B 760.76
D_BP9 N20 Input LVCMOS DDR Differential DCLK_B 760.83
D_BN11 R18 Input LVCMOS DDR Differential DCLK_B 760.78
D_BP11 T18 Input LVCMOS DDR Differential DCLK_B 760.80
D_BN13 T20 Input LVCMOS DDR Differential DCLK_B 760.78
D_BP13 R20 Input LVCMOS DDR Differential DCLK_B 760.72
D_BN15 R19 Input LVCMOS DDR Differential DCLK_B 760.80
D_BP15 T19 Input LVCMOS DDR Differential DCLK_B 760.77
DCLK_AN D19 Input LVCMOS — Differential — Input data bus A Clock (LVDS) 760.73
DCLK_AP E19 Input LVCMOS — Differential — 760.80
DCLK_BN N19 Input LVCMOS — Differential — Input data bus B Clock (LVDS) 760.72
DCLK_BP M19 Input LVCMOS — Differential — 760.80
DATA CONTROL INPUTS
SCTRL_AN F20 Input LVCMOS DDR Differential DCLK_A Data Control (LVDS) 760.74
SCTRL_AP E20 Input LVCMOS DDR Differential DCLK_A 760.70
SCTRL_BN L20 Input LVCMOS DDR Differential DCLK_B 760.83
SCTRL_BP M20 Input LVCMOS DDR Differential DCLK_B 760.78
SERIAL COMMUNICATION (SCP) AND CONFIGURATION
SCP_CLK A8 Input LVCMOS — Pulldown — —
SCP_DO A9 Output LVCMOS — — SCP_CLK —
SCP_DI A5 Input LVCMOS — Pulldown SCP_CLK —
SCP_EN B7 Input LVCMOS — Pulldown SCP_CLK —
PWRDN B9 Input LVCMOS — Pulldown — —
MICROMIRROR BIAS CLOCKING PULSE
MODE_A A4 Input LVCMOS — Pulldown — —
MBRST0 C3 Input Analog — — — Micromirror Bias Clocking Pulse "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror. —
MBRST1 D2 Input Analog — — — —
MBRST2 D3 Input Analog — — — —
MBRST3 E2 Input Analog — — — —
MBRST4 G3 Input Analog — — — —
MBRST5 E1 Input Analog — — — —
MBRST6 G2 Input Analog — — — —
MBRST7 G1 Input Analog — — — —
MBRST8 N3 Input Analog — — — —
MBRST9 M2 Input Analog — — — —
MBRST10 M3 Input Analog — — — —
MBRST11 L2 Input Analog — — — —
MBRST12 J3 Input Analog — — — —
MBRST13 L1 Input Analog — — — —
MBRST14 J2 Input Analog — — — —
MBRST15 J1 Input Analog — — — —
POWER
VCC B11, B12, B13, B16, R12, R13, R16, R17 Power Analog — — — Power for LVCMOS Logic —
VCCI A12, A14, A16, T12, T14, T16 Power Analog — — — Power supply for LVDS Interface —
VOFFSET C1, D1, M1, N1 Power Analog — — — Power for High Voltage CMOS Logic —
VSS A6, A11, A13, A15, A17, B4, B5, B8, B14, B15, B17, C2, C18, C19, F1, F2, F19, H1, H2, H3, H18, J18, K1, K2, L19, N2, P18, P19, R4, R9, R14, R15, T7, T13, T15, T17 Power Analog — — — Common return for all power inputs —
RESERVED SIGNALS (Not for use in system)
RESERVED_FC R7 Input LVCMOS — Pulldown — Pins should be connected to VSS. —
RESERVED_FD R8 Input LVCMOS — Pulldown — —
RESERVED_PFE T8 Input LVCMOS — Pulldown — —
RESERVED_STM B6 Input LVCMOS — Pulldown — —
NO_CONNECT A3, A7, A10, B2, B3, B10, E3, F3, K3, L3, P1, P2, P3, R1, R2, R3, R5, R6, R10, R11, T1, T2, T3, T4, T5, T6, T9, T10, T11 — — — — — Do not connect. —
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.
(3) Refer to Electrical Characteristics for differential termination specification.
(4) Internal Trace Length (mils) refers to the Package electrical trace length. See the DLP 0.55 XGA Chip-Set Data Manual for details regarding signal integrity considerations for end-equipment designs.