DLPS101B November   2017  – February 2023 DLP550JE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Power Interface
      2. 7.2.2 Timing
    3. 7.3 Optical Interface and System Image Quality Considerations
      1. 7.3.1 Numerical Aperture and Stray Light Control
      2. 7.3.2 Pupil Match
      3. 7.3.3 Illumination Overfill
    4. 7.4 Micromirror Array Temperature Calculation
      1. 7.4.1 Micromirror Array Temperature Calculation
    5. 7.5 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.5.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.5.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.5.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.5.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power-Up and Power-Down Procedures
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 Support Resources
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage VCC = 3.0 V, IOH = –20 mA 2.4 V
VOL Low-level output voltage VCC = 3.6 V, IOL = 15 mA 0.4 V
IOZ High impedance output current VCC = 3.6 V 10 µA
IIL Low-level input current VCC = 3.6 V, VI = 0 V –60 µA
IIH High-level input current(1) VCC = 3.6 V, VI = VCC 200 µA
ICC Current into VCC pin VCC = 3.6 V 531 mA
ICCI Current into VCC1 pin(2) VCCI = 3.6 V 374 mA
IOFFSET Current into VOFFSET pin(3) VOFFSET = 8.75 V 25 mA
ZIN Internal Differential Impedance 95 105 Ω
ZLINE Line Differential Impedance (PWB or Trace) 90 100 110 Ω
CI Input capacitance(1) f = 1 MHz 10 pF
CO Output capacitance(1) f = 1 MHz 10 pF
CIM Input capacitance for MBRST[0:15] pins f = 1 MHz 160 210 pF
(1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins
(2) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limits listed in the GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.html#GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit in GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.html#GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7.