DLPS200B July   2020  – April 2021 DLP5530S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     Illumination Overfill Diagram
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     Electrical and Timing Diagrams
    10. 6.8  Switching Characteristics
    11.     LPSDR and Test Load Circuit Diagrams
    12. 6.9  System Mounting Interface Loads
    13.     System Interface Loads Diagram
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     Array Physical Characteristics Diagram
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYS|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Please refer to the DLPC230S-Q1 and TPS99000S-Q1 data sheets for specific PCB layout and routing guidelines. For specific DMD PCB guidelines, use the following:

  • Match lengths for the LS_WDATA and LS_CLK signals.
  • Minimize vias, layer changes, and turns for the HS bus signals.
  • Minimum of two 220-nF decoupling capacitors close to VBIAS.
  • Minimum of two 220-nF decoupling capacitors close to VRESET.
  • Minimum of two 220-nF decoupling capacitors close to VOFFSET.
  • Minimum of four 100-nF decoupling capacitors close to VDDI and VDD.
  • Temperature diode pins

    The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411 temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to noise. Please see the TMP411 data sheet for specific routing recommendations.