DLPS040A October   2014  – October 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Typical Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Mirror Park Sequence Requirements
      1. 9.3.1 DLPC900
      2. 9.3.2 DLPC910
    4. 9.4 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PCB Recommendations
    2. 10.2 Layout Example
      1. 10.2.1 Board Stack and Impedance Requirements
        1. 10.2.1.1 Power Planes
        2. 10.2.1.2 LVDS Signals
        3. 10.2.1.3 Critical Signals
        4. 10.2.1.4 Flex Connector Plating
        5. 10.2.1.5 Device Placement
        6. 10.2.1.6 Device Orientation
        7. 10.2.1.7 Fiducials
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FLQ|203
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Requirements

9.1 DMD Power Supply Requirements

The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the digital controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. VSS must also be connected. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 18.

9.2 DMD Power Supply Power-Up Procedure

  • During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD.
  • During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start after VOFFSET.
  • During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 18.
  • During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at operating voltages listed in Recommended Operating Conditions.

9.3 DMD Mirror Park Sequence Requirements

9.3.1 DLPC900

For correct power down operation of the DLP6500 DMD with the DLPC900, the following power down procedure must be executed.

Prior to an anticipated power removal, the controlling applications processor must command the DLPC900 to enter Standby mode by using the Power Mode command and then wait for a minimum of 20 ms to allow the DLPC900 to complete the power down procedure. This procedure will assure the mirrors are in a flat state. Following this procedure, the power can be safely removed.

In the event of an unanticipated power loss, the power management system must detect the input power loss, command the DLPC900 to enter Standby mode by using the Power Mode command, and then maintain all operating power levels of the DLPC900 and the DLP6500 DMD for a minimum of 20 ms to allow the DLPC900 to complete the power down procedure. Following this procedure, the power can be allowed to fall below safe operating levels. Refer to the DLPC900 datasheet for more details on power down requirements.

In both anticipated power down and unanticipated power loss, the DLPC900 is commanded over the USB/I2C interface, and then the DLPC900 loades the correct power down sequence to the DMD. Communicating over the USB/I2C and loading the power down sequence accounts for most of the 20 ms. Compared to the DLPC910, the controlling processor only needs to assert the PWR_FLOAT pin and wait for a minimum of 500 µs.

The controlling applications processor can resume normal operations by commanding the DLPC900 to enter Normal mode. See Power Mode command in the DLPC900 Software Programmer’s Guide DLPU018 for a description of this command.

9.3.2 DLPC910

For correct power down operation of the DLP6500 DMD with the DLPC910, the following power down procedure must be executed.

Prior to an anticipated power removal, assert PWR_FLOAT to the DLPC910 for a minimum of 500 μs to allow the DLPC910 to complete the power down procedure. This procedure will assure the DMD mirrors are in a flat state. Following this procedure, the power can be safely removed.

In the event of an unanticipated power loss, the power management system must detect the input power loss, assert PWR_FLOAT to the DLPC910, and maintain all operating power levels of the DLPC910 and the DLP6500 DMD for a minimum of 500 μs to allow the DLPC910 to complete the power down procedure. Refer to the DLPC910 datasheet for more details on power down requirements.

To restart after assertion of PWR_FLOAT without removing power, the DLPC910 must be reset by setting CTRL_RSTZ low (logic 0) for 50 ms, and then back to high (logic 1), or power to the DLPC910 must be cycled.

9.4 DMD Power Supply Power-Down Procedure

Refer to DMD Mirror Park Sequence Requirements for the power down procedure.

  • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. Refer to Table 5.
  • During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 18.
  • During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions.
DLP6500 Power_Down_Procedure.gif Figure 18. DMD Power Supply Sequencing Requirements
  1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
  2. LVDS signals are less than the input differential voltage (VID) maximum specified in Recommended Operating Conditions. During power-down, LVDS signals are less than the high level input voltage (VIH) maximum specified in Recommended Operating Conditions.
  3. When system power is interrupted, the DLP digital controller initiates a power-down sequence that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to disable VBIAS, VOFFSET, and VRESET, respectfully.
  4. Refer to DMD Power Down Sequence Requirements.
  5. Figure not to scale. Details have been omitted for clarity. Refer Recommended Operating Conditions.
  6. Refer to DMD Mirror Park Sequence Requirements for details on powering down the DMD.

Table 5. DMD Power-Down Sequence Requirements

PARAMETER MIN MAX UNIT
VBIAS Supply voltage level during power–down sequence 4.0 V
VOFFSET Supply voltage level during power–down sequence 4.0 V
VRESET Supply voltage level during power–down sequence –4.0 0.5 V