DLPS040A October   2014  – October 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Typical Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Mirror Park Sequence Requirements
      1. 9.3.1 DLPC900
      2. 9.3.2 DLPC910
    4. 9.4 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PCB Recommendations
    2. 10.2 Layout Example
      1. 10.2.1 Board Stack and Impedance Requirements
        1. 10.2.1.1 Power Planes
        2. 10.2.1.2 LVDS Signals
        3. 10.2.1.3 Critical Signals
        4. 10.2.1.4 Flex Connector Plating
        5. 10.2.1.5 Device Placement
        6. 10.2.1.6 Device Orientation
        7. 10.2.1.7 Fiducials
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FLQ|203
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1)
SUPPLY VOLTAGES MIN MAX UNIT
VCC Supply voltage for LVCMOS core logic (2) –0.5 4 V
VCCI Supply voltage for LVDS receivers (2) –0.5 4 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(2) (3) –0.5 9 V
VBIAS Supply voltage for micromirror electrode (2) –0.5 17 V
VRESET Supply voltage for micromirror electrode(2) –11 0.5 V
| VCC – VCCI | Supply voltage delta (absolute value) (4) 0.3 V
| VBIAS – VOFFSET | Supply voltage delta (absolute value)(5) 8.75 V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins (2) –0.5 VCC + 0.3 V
Input voltage for all other LVDS input pins(2) –0.5 VCCI + 0.3 V
|VID| Input differential voltage (absolute value)(2) (6) 700 mV
IID Input differential current (7) 7 mA
CLOCKS
ƒclock Clock frequency for LVDS interface, DCLK_A 440 MHz
Clock frequency for LVDS interface, DCLK_B 440
ENVIRONMENTAL
TARRAY Array temperature: operational(8)(9) 0 90 °C
Array temperature: non-operational(8)(9) -40 90
TWINDOW Window temperature: operational 0 65 °C
Window temperature: non–operational -40 90
| TDELTA| Absolute termperature delta between the window test point and the ceramic test point TP1 (10) 10 °C
RH Relative Humidity, operating and non–operating 95 %
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.
(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(3) VOFFSET supply transients must fall within specified voltages.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information.
(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential temperature, or illumination power density will reduce device lifetime. Refer to ESD Ratings.
(9) The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1 (TP1) in Figure 15.
(10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15.

6.2 Storage Conditions

applicable before the DMD is installed in the final product
MIN MAX UNIT
TDMD Storage temperature range (non-operating) –40 80 °C
RH Relative Humidity (non-condensing) 95%

6.3 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLY VOLTAGES(1)(2)
VCC Supply voltage for LVCMOS core logic 3.0 3.3 3.6 V
VCCI Supply voltage for LVDS receivers 3.0 3.3 3.6 V
VOFFSET Supply voltage for HVCMOS and micromirror electrodes(3) 8.25 8.5 8.75 V
VBIAS Supply voltage for micromirror electrodes 15.5 16 16.5 V
VRESET Mirror electrode voltage –9.5 –10 –10.5 V
| VCCI–VCC | Supply voltage delta (absolute value) (4) 0.3 V
| VBIAS–VOFFSET | Supply voltage delta (absolute value) (5) 8.75 V
LVCMOS PINS
VIH High level Input voltage(6) 1.7 2.5 VCC + 0.3 V
VIL Low level Input voltage(6) –0.3 0.7 V
IOH High level output current at VOH = 2.4 V –20 mA
IOL Low level output current at VOL = 0.4 V 15 mA
TPWRDNZ PWRDNZ pulse width(7) 10 ns
SCP INTERFACE(5)
ƒclock SCP clock frequency(8) 500 kHz
tSCP_SKEW Time between valid SCPDI and rising edge of SCPCLK(9) –800 800 ns
tSCP_DELAY Time between valid SCPDO and rising edge of SCPCLK(9) 700 ns
tSCP_BYTE_INTERVAL_ Time between consecutive bytes 1 µs
tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK 30 ns
tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 µs
tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tri-state) 1.5 ns
ƒclock SCP circuit clock oscillator frequency(10) 9.6 11.1 MHz
LVDS INTERFACE
ƒclock Clock frequency DCLK 400 MHz
| VID | Input differential voltage (absolute value)(11) 100 400 600 mV
VCM Common mode(11) 1200 mV
VLVDS LVDS voltage(11) 0 2000 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 10 ns
ZIN Internal differential termination resistance 95 105 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL(12) For Illumination Source Between 420 nm and 700 nm
TARRAY Array temperature, Long-term operational(13)(14)(16) 10 40 to 65(15) °C
Array temperature, Short-term operational(13)(14)(17) 0 10 °C
TWINDOW Window Temperature test points TP2 and TP3, Long-term operational.(16) 10 65 °C
|TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1  (18) 10 °C
ILLVIS Illumination, wavelengths between 420 nm and 700 nm Thermally Limited(19) mW/cm2
RH Relative Humidity (non-condensing) 95%
ENVIRONMENTAL(12) For Illumination Source Between 400 nm and 420 nm
TARRAY Array temperature, Long-term operational(13)(14)(16) 20 30(15) °C
Array temperature, Short-term operational(13)(14)(17) 0 20 °C
TWINDOW Window Temperature test points TP2 and TP3, Long-term operational.(16) 30 °C
|TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1  (18) 10 °C
ILLVIS Illumination, wavelengths between 400 and 420 nm 10 W/cm2
RH Relative Humidity (non-condensing) 95%
ENVIRONMENTAL(12) For Illumination Source <400 nm and >700 nm
TARRAY Array temperature, Long-term operational(13)(14)(16) 10 40 to 65(15) °C
Array temperature, Short-term operational(13)(14)(17) 0 10 °C
TWINDOW Window Temperature test points TP2 and TP3, Long-term operational.(16) 10 65 °C
|TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1  (18) 10 °C
ILLUV Illumination, wavelength < 400 nm 0.68 mW/cm2
ILLIR Illumination, wavelength > 700 nm 10 mW/cm2
RH Relative Humidity (non-condensing) 95%
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) All voltages are referenced to common ground VSS.
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information.
(6) Tester Conditions for VIH and VIL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% to 20%)
(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.
(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Refer to Figure 3.
(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(11) Refer to Figure 4, Figure 5, and Figure 6.
(12) Optimal, long-term performance and optical effciency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
(13) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.
(14) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 15 and the package thermal resistance Thermal Information using Micromirror Array Temperature Calculation.
(15) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(16) Long-term is defined as the usable life of the device.
(17) Array and Window temperatures beyond those specified as long-term are recommended for short-term conditions only (power- up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(18) Temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in Figure 15.
DLP6500 mirrorlanding_graph_dlps036.gif Figure 1. Max Recommended DMD Temperature – Derating Curve

6.5 Thermal Information

THERMAL METRIC(1) DLP6500 UNIT
FLQ (CLGA)
203 PINS
Active Area to Case Ceramic Thermal resistance (1) 0.7 °C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH High-level output voltage VCC = 3 V, IOH = –20 mA 2.4 V
VOL Low level output voltage VCC = 3.6 V, IOL = 15 mA 0.4 V
IIH High–level input current(2)(3) VCC = 3.6 V, VI = VCC 250 µA
IIL Low level input current VCC = 3.6 V, VI = 0 –250 µA
IOZ High–impedance output current VCC = 3.6 V 10 µA
CURRENT
ICC Supply current(4) VCC = 3.6 V 1076 mA
ICCI Supply current(4) VCCI = 3.6 V 518
IOFFSET Supply current(5) VOFFSET = 8.75 V 4 mA
IBIAS Supply current(5) VBIAS = 16.5 V 14
IRESET Supply current VRESET = –10.5 V 11 mA
ITOTAL Supply current Total Sum 1623
POWER
PCC Supply power dissipation VCC = 3.6 V 3874 mW
PCCI VCCI = 3.6 V 1865
POFFSET VOFFSET = 8.75 V 35
PBIAS VBIAS = 16.5 V 231
PRESET VRESET = –10.5 V 116
PTOTAL Supply power dissipation(6) Total Sum 6300
CAPACITANCE
CI Input capacitance ƒ = 1 MHz 10 pF
CO Output capacitance ƒ = 1 MHz 10 pF
CM Reset group capacitance MBRST(14:0) ƒ = 1 MHz; 1920 × 72 micromirrors 330 390 pF
(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.
(3) LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and Functions to determine pull-up or pull-down configuration used.
(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(6) Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination source. See the Micromirror Array Temperature Calculation.

6.7 Timing Requirements

Over Recommended Operating Conditions unless otherwise noted.
DESCRIPTION(1) MIN TYP MAX UNIT
SCP INTERFACE(2)
tr Rise time 20% to 80% 200 ns
tƒ Fall time 80% to 20% 200 ns
LVDS INTERFACE(2)
tr Rise time 20% to 80% 100 400 ps
tƒ Fall time 80% to 20% 100 400 ps
LVDS CLOCKS(3)
tc Cycle time DCLK_A, 50% to 50% 2.5 ns
DCLK_B, 50% to 50% 2.5
tw Pulse duration DCLK_A, 50% to 50% 1.19 1.25 ns
DCLK_B, 50% to 50% 1.19 1.25
LVDS INTERFACE(3)
tsu Setup time D_A(15:0) before rising or falling edge of DCLK_A 0.2 ns
D_B(15:0) before rising or falling edge of DCLK_B 0.2
tsu Setup time SCTRL_A before rising or falling edge of DCLK_A 0.2 ns
SCTRL_B before rising or falling edge of DCLK_B 0.2
th Hold time D_A(15:0) after rising or falling edge of DCLK_A 0.5 ns
D_B(15:0) after rising or falling edge of DCLK_B 0.5
th Hold time SCTRL_A after rising or falling edge of DCLK_A 0.5 ns
SCTRL_B after rising or falling edge of DCLK_B 0.5
LVDS INTERFACE(4)
tskew Skew time Channel B relative to Channel A Channel A includes the following LVDS pairs:
DCLK_AP and DCLK_AN
SCTRL_AP and SCTRL_AN
D_AP(15:0) and D_AN(15:0)		 –1.25 1.25 ns
Channel B includes the following LVDS pairs:
DCLK_BP and DCLK_BN
SCTRL_BP and SCTRL_BN
D_BP(15:0) and D_BN(15:0)
(1) Refer to Pin Configuration and Functions for pin details.
(2) Refer to Figure 7.
(3) Refer to Figure 8.
(4) Refer to Figure 9.

Timing Diagrams

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 2 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation section.

DLP6500 Test_Load_Circuit.gif Figure 2. Test Load Circuit
DLP6500 SCP_Timing_Parameters.gif
Not to scale.
Refer to SCP Interface section of the Recommended Operating Conditions table.
Figure 3. SCP Timing Parameters
DLP6500 LVDS_Voltage_Definitions_references.gif
Refer to the LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for a list of LVDS pins.
Figure 4. LVDS Voltage Definitions (References)
DLP6500 LVDS_Voltage_parameters.gif
Not to scale.
Refer to the LVDS Interface section of the Recommended Operating Conditions table.
Figure 5. LVDS Voltage Parameters
DLP6500 LVDS_Voltage_Definitions_Parameters.gif
Refer to LVDS Interface section of the Recommended Operating Conditions table
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 6. LVDS Equivalent Input Circuit
DLP6500 Rise_Time_Fall_Time.gif
Not to scale.
Refer to the Timing Requirements table.
Refer to Pin Configuration and Functions for list of LVDS pins and SCP pins.
Figure 7. Rise Time and Fall Time
DLP6500 LVDS_Timing_Requirements.gif
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 8. Timing Requirement Parameter Definitions
DLP6500 LVDS_Channel_Skew.gif
Not to scale.
Refer to LVDS INTERFACE in the Timing Requirements table.
Figure 9. LVDS Interface Channel Skew Definition

6.8 Typical Characteristics

When the DMD is controlled by the DLPC900, the digital controller has four modes of operation.
  1. Video Mode
  2. Video Pattern Mode
  3. Pre-Stored Pattern Mode
  4. Pattern On-The-Fly Mode

In video mode, the video source is displayed on the DMD at the rate of the incoming video source.

In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1.

Table 1. DLPC900 with DLP6500 Pattern Rate versus Bit Depth

BIT DEPTH VIDEO PATTERN MODE (Hz) PRE-STORED or PATTERN ON-THE-FLY MODE (Hz)
1 2880 9523
2 1440 3289
3 960 2638
4 720 1364
5 480 823
6 480 672
7 360 500
8 247 247

When the DLP6500 DMD is controlled by the DLPC910, the controller operates in pattern mode only. With proper illumination modulation, bit depths greater than 1 can be achieved. Table Table 2 shows the pattern rates for each bit depth.

Table 2. DLPC910 with DLP6500 Pattern Rate versus Bit Depth

BIT DEPTH PATTERN RATE (Hz)
1 11574
2 5787
3 3858
4 2893
5 2315
6 1929
7 1653
8 1446

6.9 System Mounting Interface Loads

PARAMETER MIN NOM MAX UNIT
Maximum system mounting interface load to be applied to the: Thermal Interface area (See Figure 10) 25 lbs
Electrical Interface area 95 lbs
Datum “A” Interface area(1) 90 lbs
(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum “A” area (95 + 25 – Datum “A).
DLP6500 typa_a_loads.gif Figure 10. System Mounting Interface Loads

6.10 Micromirror Array Physical Characteristics

PARAMETER VALUE UNIT
M Number of active columns See Figure 11 1920 micromirrors
N Number of active rows 1080 micromirrors
P Micromirror (pixel) pitch 7.56 µm
Micromirror active array width M × P 14.5152 mm
Micromirror active array height N × P 8.1648 mm
Micromirror active border Pond of micromirror (POM)(1) 14 micromirrors /side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.
DLP6500 Micromirror_Array_Physical.gif
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 11. Micromirror Array Physical Characteristics

6.11 Micromirror Array Optical Characteristics

See Optical Interface and System Image Quality for important information.

PARAMETER CONDITIONS MIN NOM MAX UNIT
α Micromirror tilt angle DMD landed state (1) 12 °
β Micromirror tilt angle tolerance(1) (2)(3)(4)(5) –1 1 °
Micromirror tilt direction(5)(6) (7) Figure 12 44 45 46 °
Number of out-of-specification micromirrors (7) Adjacent micromirrors 0 micromirrors
Non-adjacent micromirrors 10
Micromirror crossover time (8)(9) Typical performance 2.5 μs
DMD efficiency within the wavelength range 400 nm to 420 nm(10) 68%
DMD photopic efficiency within the wavelength range 420 nm to 700 nm(10) 66%
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the specified Micromirror Switching Time.
(8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.
(9) Performance as measured at the start of life.
(10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.
DLP6500 Micromirror_Landed_Orientation.gif
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 12. Micromirror Landed Orientation and Tilt

6.12 Window Characteristics

PARAMETER(1) CONDITIONS MIN TYP MAX UNIT
Window material designation Corning 7056
Window refractive index at wavelength 589 nm 1.487
Window aperture(2) See(2)
Illumination overfill(3) See(3)
Window transmittance, single–pass through both surfaces and glass (4) At wavelength 405 nm. Applies to 0° and 24° AOI only. 95%
Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI. 97%
Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI. 97%
(1) See Window Characteristics and Optics for more information.
(2) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical ICD in section Mechanical, Packaging, and Orderable Information.
(3) Refer to Illumination Overfill.
(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP® DMD Window.

6.13 Chipset Component Usage Specification

The DLP6500 is a component of one or more DLP chipsets. Reliable function and operation of the DLP6500 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD.