DLPS095B November   2017  – November 2024 DLP650LE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  Window Characteristics
    10. 5.10 System Mounting Interface Loads
    11. 5.11 Micromirror Array Physical Characteristics
    12. 5.12 Micromirror Array Optical Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
SUPPLY VOLTAGES
VCC Supply voltage for LVCMOS core logic(2) –0.5 4 V
VCCI Supply voltage for LVDS Interface(2) –0.5 4 V
VOFFSET Micromirror Electrode and HVCMOS voltage(2)(3) –0.5 9 V
VMBRST Input voltage for MBRST(15:0)(2) –28 28 V
|VCCI – VCC| Supply voltage delta (absolute value)(4) 0.3 V
INPUT VOLTAGES
Input voltage for all other input pins(2) –0.5 VCC + 0.3 V
|VID| Input differential voltage (absolute value)(5) 700 mV
CLOCKS
ƒCLOCK Clock frequency for LVDS interface, DCLK_A 400 MHz
ƒCLOCK Clock frequency for LVDS interface, DCLK_B 400 MHz
ENVIRONMENTAL
TARRAY and TWINDOW Temperature, operating(6) 0 90 °C
Temperature, non–operating(6) –40 90 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(7) 30 °C
TDP Dew point temperature, operating and non–operating (noncondensing) 81 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are referenced to common ground VSS. VCC, VCCI, VOFFSET, and VSS (GND) power supplies are all required for all DMD operating modes.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.
(5) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS differential inputs must not exceed |VID| = 700mV or damage may result to the internal termination resistors.
(6) The highest temperature of the active array (as calculated using Section 6.6) or of any point along the window edge as defined in Figure 6-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 6-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, then that point needs to be used.
(7) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, then that point needs to be used.