DLPS095 Data sheet

DLPS095B November 2017 – November 2024 DLP650LE

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FYL|149
- MCLG035

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
VOLTAGE SUPPLY
V_CC	Supply voltage for LVCMOS core logic⁽¹⁾	3.0	3.3	3.6	V
V_CCI	Supply voltage for LVDS interface⁽¹⁾	3.0	3.3	3.6	V
V_OFFSET	Micromirror electrode and HVCMOS voltage⁽¹⁾⁽²⁾	8.25	8.5	8.75	V
V_MBRST	Micromirror bias / reset voltage⁽¹⁾	–27		26.5	V
\|V_CC – V_CCI\|	Supply voltage delta (absolute value)⁽³⁾		0	0.3	V
LVCMOS INTERFACE
V_IH	Input high voltage	1.7	2.5	V_CC + 0.3	V
V_IL	Input low voltage	–0.3		0.7	V
I_OH	High level output current			–20	mA
I_OL	Low level output current			15	mA
t_PWRDNZ	PWRDNZ pulse width⁽⁴⁾	10			ns
SCP INTERFACE
ƒ_SCPCLK	SCP clock frequency⁽⁵⁾	50		500	kHz
t_{SCP_PD}	Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO⁽⁶⁾	0		900	ns
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling-edge)⁽⁶⁾	800			ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling-edge)⁽⁶⁾	900			ns
t_{SCP_NEG_ENZ}	Time between falling-edge of SCPENZ and the rising-edge of SCPCLK.⁽⁵⁾	1			us
_{SCP_POS_ENZ}	Time between falling-edge of SCPCLK and the rising-edge of SCPENZ	1			us
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tristate)			192/ƒ_DCLK	s
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			1/ƒ_scpclk
t_{r_SCP}	Rise time for SCP signals			200	ns
t_{f_SCP}	Fall time for SCP signals			200	ns
LVDS INTERFACE
ƒ_CLOCK	Clock frequency for LVDS interface (all channels), DCLK⁽⁷⁾		320	330	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽⁸⁾	100	400	600	mV
V_CM	Common mode voltage⁽⁸⁾		1200		mV
V_LVDS	LVDS voltage⁽⁸⁾	0		2000	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	85	90	95	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long-term operational⁽⁹⁾⁽¹⁰⁾⁽¹¹⁾	10		40 to 70⁽¹²⁾	°C
T_ARRAY	Array temperature, short-term operational, 500 hr max⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_WINDOW	Window temperature (all part numbers except *1280-6434B)⁽¹⁴⁾	10		90	°C
T_WINDOW	Window temperature (part number 1280-6434B)⁽¹⁴⁾	10		85
T_{\|DELTA \|}	Absolute temperature delta between any point on the window edge and the ceramic test point TP1⁽¹⁵⁾			26	°C
T_{DP -AVG}	Average dew point average temperature (non-condensing)⁽¹⁶⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁷⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
SOLID STATE ILLUMINATION
ILL_UV	Illumination power at wavelengths < 410nm⁽⁹⁾⁽¹⁹⁾			10	mW/cm2
ILL_VIS	Illumination power at wavelengths ≥ 410nm and ≤ 800nm⁽¹⁸⁾⁽¹⁹⁾			23.7	W/cm2
ILL_IR	Illumination power at wavelengths > 800nm⁽¹⁹⁾			10	mW/cm2
ILL_BLU	Illumination power at wavelengths ≥ 410nm and ≤ 475nm⁽¹⁸⁾⁽¹⁹⁾			7.5	W/cm2
ILL_BLU1	Illumination power at wavelengths ≥ 410nm and ≤ 440nm⁽¹⁸⁾⁽¹⁹⁾			1.3	W/cm2
LAMP ILLUMINATION
ILL_UV	Illumination power at wavelengths < 395nm⁽⁹⁾⁽¹⁹⁾			2.0	mW/cm2
ILL_VIS	Illumination power at wavelengths ≥ 395nm and ≤ 800nm⁽¹⁸⁾⁽¹⁹⁾			23.7	W/cm2
ILL_IR	Illumination power at wavelengths > 800nm⁽¹⁹⁾			10	mW/cm2

(1) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESET power supplies are all required for proper DMD operation. V_SS must also be connected.

(2) V_OFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |V_CCI – V_CC| must be less than specified limit. See Section 8.

(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.

(5) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(6) See Figure 5-2.

(7) See LVDS Timing Requirements in Section 5.8 and Figure 5-6.

(8) Refer to Figure 5-5.

(9) Simultaneous exposure of the DMD to the maximum Section 5.4 for temperature and UV illumination reduces device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 6-1 and the package Section 5.5 using the calculation in Section 6.6.

(11) Long-term is defined as the usable life of the device.

(12) Per Figure 5-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 6.8 for a definition of micromirror landed duty cycle.

(13) Short-term is defined as cumulative time over the usable life of the device.

(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 6-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(16) The average over time (including storage and operating) that the device is not in the "elevated dew point temperature range."

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(18) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(19) To calculate see Section 6.7.

DLP650LE Maximum Recommended Array
Temperature—Derating Curve

Figure 5-1 Maximum Recommended Array Temperature—Derating Curve