DLPS095B November   2017  – November 2024 DLP650LE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  Window Characteristics
    10. 5.10 System Mounting Interface Loads
    11. 5.11 Micromirror Array Physical Characteristics
    12. 5.12 Micromirror Array Optical Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DLP650LE FYL Package149-Pin CLGABottom ViewFigure 4-1 FYL Package149-Pin CLGABottom View
Table 4-1 Pin Functions
PINNET LENGTH (mils)SIGNALTYPE(1)DESCRIPTION
NAMENO.
DATA INPUTS
D_AN(1)G20711.64LVDSILVDS pair for Data Bus A
D_AN(3)H19711.60
D_AN(5)F18711.60
D_AN(7)E18711.60
D_AN(9)C20711.60
D_AN(11)B18711.60
D_AN(13)A20711.60
D_AN(15)B19711.58
D_AP(1)H20711.66
D_AP(3)G19711.61
D_AP(5)G18711.59
D_AP(7)D18711.60
D_AP(9)D20711.59
D_AP(11)A18711.58
D_AP(13)B20711.59
D_AP(15)A19711.59
D_BN(1)K20711.61LVDSILVDS pair for Data Bus B
D_BN(3)J19711.59
D_BN(5)L18711.59
D_BN(7)M18711.6
D_BN(9)P20711.6
D_BN(11)R18711.59
D_BN(13)T20711.59
D_BN(15)R19711.59
D_BP(1)J20711.61
D_BP(3)K19711.6
D_BP(5)K18711.58
D_BP(7)N18711.58
D_BP(9)N20711.6
D_BP(11)T18711.61
D_BP(13)R20711.59
D_BP(15)T19711.6
DCLK_AND19711.59ILVDS pair for Data Clock A
DCLK_APE19711.59
DCLK_BNN19711.6ILVDS pair for Data Clock B
DCLK_BPM19711.61
DATA CONTROL INPUTS
SCTRL_ANF20711.62ILVDS pair for Serial Control (Sync) A
SCTRL_APE20711.6
SCTRL_BNL20711.59ILVDS pair for Serial Control (Sync) B
SCTRL_BPM20711.59
MICROMIRROR BIAS RESET INPUTS
MBRST(0)C3507.20INonlogic compatible Micromirror Bias Reset signals. Connected directly to the array of pixel micromirrors. Used to hold or release the micromirrors. Bond Pads connect to an internal pulldown resistor.
MBRST(1)D2576.83
MBRST(2)D3545.78
MBRST(3)E2636.33
MBRST(4)G3618.42
MBRST(5)E1738.25
MBRST(6)G2718.82
MBRST(7)G1777.04
MBRST(8)N3543.29
MBRST(9)M2612.93
MBRST(10)M3580.97
MBRST(11)L2672.43
MBRST(12)J3653.61
MBRST(13)L1764.00
MBRST(14)J2764.37
MBRST(15)J1813.14
SCP CONTROL
SCPCLKA8ISerial Communications Port Clock. Bond Pad connects to an internal pulldown circuit.
SCPDIA5ISerial Communications Port Data. Bond Pad connects to an internal pulldown circuit.
SCPENZB7IActive low serial communications port enable. Bond pad connects to an internal pulldown circuit.
SCPDOA9OSerial communications port output
OTHER SIGNALS
EVCCA3PDo not connect on the DLP system board.
MODE_AA4415.1IData Bandwidth Mode Select. Bond Pad connects to an internal pulldown circuit. Refer to Table 4 for DLP system board connection information.
PWRDNZB9110.38IActive Low Device Reset. Bond Pad connects to an internal pulldown circuit.
POWER
VCC(2)B11, B12, B13, B16, R12, R13, R16, R17PPower supply for low voltage CMOS logic. Power supply for normal high voltage at micromirror address electrodes
VCCI(2)A12, A14, A16, T12, T14, T16PPower supply for low voltage CMOS LVDS interface
VOFFSET(2)C1, D1, M1, N1PPower supply for high voltage CMOS logic. Power supply for stepped high voltage at micromirror address electrodes
VSS (Ground)(3)A6, A11, A13, A15, A17, B4, B5, B8, B14, B15, B17, C2, C18, C19, F1, F2, F19, H1, H2, H3, H18, J18, K1, K2, L19, N2, P18, P19, R4, R9, R14, R15, T7, T13, T15, T17PCommon return for all power
RESERVED SIGNALS
RESERVED_FCR740.64IConnect to GND on the DLP system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_FDR894.37IConnect to GND on the DLP system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_PFET850.74IConnect to ground on the DLP system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_STMB6IConnect to GND on the DLP system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_TP0R1093.3IDo not connect on the DLP system board.
RESERVED_TP1T11263.74IDo not connect on the DLP system board.
RESERVED_TP2R11281.47IDo not connect on the DLP system board.
RESERVED_BAT10148.85ODo not connect on the DLP system board.
RESERVED_BBA10105.28ODo not connect on the DLP system board.
RESERVED_RA1T9ODo not connect on the DLP system board.
RESERVED_RB1A7ODo not connect on the DLP system board.
RESERVED_TSB10145.42ODo not connect on the DLP system board.
RESERVED_A(0)T2NCDo not connect on the DLP system board.
RESERVED_A(1)T3
RESERVED_A(2)R3
RESERVED_A(3)T4
RESERVED_M(0)R2NCDo not connect on the DLP system board.
RESERVED_M(1)P1NCDo not connect on the DLP system board.
RESERVED_S(0)T1NCDo not connect on the DLP system board.
RESERVED_S(1)R1NCDo not connect on the DLP system board.
RESERVED_IRQZT6NCDo not connect on the DLP system board.
RESERVED_OEZR5NCDo not connect on the DLP system board.
RESERVED_RSTZR6NCDo not connect on the DLP system board.
RESERVED_STRT5NCDo not connect on the DLP system board.
RESERVED_STRT5NCDo not connect on the DLP system board.
RESERVED_VBE3, F3, K3, L3NCDo not connect on the DLP system board.
RESERVED_VRB2, B3, P2, P3NCDo not connect on the DLP system board.
(1) I = Input, O = Output, G = Ground, A = Analog, P = Power, NC = No Connect.
(2) Power supply pins required for all DMD operating modes are VSS, VBIAS, VCC, VCCI, VOFFSET, and VRESET.
(3) VSS must be connected for proper DMD operation.