The DLP650TE digital micromirror device (DMD) is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM) that enables bright 4K UHD display systems. The DLP® Products 0.65-inch 4K UHD chipset is composed of the DMD, DLPC7540 display controller, and DLPA100 Power and motor driver. The compact physical size of the chipset provides a complete system solution that enables small form factor 4K UHD displays.
The DMD ecosystem includes established resources to help the user accelerate the design cycle, visit the DLP® Products third-party search tools to find approved optical module manufacturers and third party providers.
Visit Getting Started With TI DLP Display Technology to learn more about how to start designing with the DMD.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE |
---|---|---|
DLP650TE | FYP(149) | 32.2mm × 22.3mm |
PIN | TYPE(1) | PIN DESCRIPTION | TRACE LENGTH (mm) | |
---|---|---|---|---|
NAME | PAD ID | |||
D_AP(0) | J1 | I | High-speed differential data pair lane A0 | 18.09088 |
D_AN(0) | H1 | I | High-speed differential data pair lane A0 | 18.0916 |
D_AP(1) | G1 | I | High-speed differential data pair lane A1 | 18.11696 |
D_AN(1) | F1 | I | High-speed differential data pair lane A1 | 18.11641 |
D_AP(2) | A3 | I | High-speed differential data pair lane A2 | 11.11822 |
D_AN(2) | A4 | I | High-speed differential data pair lane A2 | 11.11745 |
D_AP(3) | D2 | I | High-speed differential data pair lane A3 | 12.04461 |
D_AN(3) | C2 | I | High-speed differential data pair lane A3 | 12.04491 |
D_AP(4) | F2 | I | High-speed differential data pair lane A4 | 15.1345 |
D_AN(4) | E2 | I | High-speed differential data pair lane A4 | 15.13457 |
D_AP(5) | A5 | I | High-speed differential data pair lane A5 | 12.80888 |
D_AN(5) | A6 | I | High-speed differential data pair lane A5 | 12.80825 |
D_AP(6) | A7 | I | High-speed differential data pair lane A6 | 6.34763 |
D_AN(6) | A8 | I | High-speed differential data pair lane A6 | 6.34706 |
D_AP(7) | A9 | I | High-speed differential data pair lane A7 | 4.45653 |
D_AN(7) | A10 | I | High-speed differential data pair lane A7 | 4.45875 |
DCLK_AP | C1 | I | High-speed differential clock A | 15.08029 |
DCLK_AN | D1 | I | High-speed differential clock A | 15.07977 |
D_BP(0) | A11 | I | High-speed differential data pair lane B0 | 4.06642 |
D_BN(0) | A12 | I | High-speed differential data pair lane B0 | 4.06697 |
D_BP(1) | A13 | I | High-speed differential data pair lane B1 | 6.42676 |
D_BN(1) | A14 | I | High-speed differential data pair lane B1 | 6.42716 |
D_BP(2) | A15 | I | High-speed differential data pair lane B2 | 11.90485 |
D_BN(2) | A16 | I | High-speed differential data pair lane B2 | 11.90509 |
D_BP(3) | A18 | I | High-speed differential data pair lane B3 | 13.80223 |
D_BN(3) | A19 | I | High-speed differential data pair lane B3 | 13.80269 |
D_BP(4) | D19 | I | High-speed differential data pair lane B4 | 12.45294 |
D_BN(4) | C19 | I | High-speed differential data pair lane B4 | 12.45252 |
D_BP(5) | H20 | I | High-speed differential data pair lane B5 | 15.7909 |
D_BN(5) | J20 | I | High-speed differential data pair lane B5 | 15.79026 |
D_BP(6) | D20 | I | High-speed differential data pair lane B6 | 11.02899 |
D_BN(6) | E20 | I | High-speed differential data pair lane B6 | 11.02947 |
D_BP(7) | F20 | I | High-speed differential data pair lane B7 | 14.7517 |
D_BN(7) | G20 | I | High-speed differential data pair lane B7 | 14.75085 |
DCLK_BP | B17 | I | High-speed differential clock B | 9.17864 |
DCLK_BN | B18 | I | High-speed differential clock B | 9.17821 |
LS_WDATA_P | T10 | I | LVDS Data | 11.27905 |
LS_WDATA_N | R11 | I | LVDS Data | 6.76474 |
LS_CLK_P | R9 | I | LVDS CLK | 13.5461 |
LS_CLK_N | R10 | I | LVDS CLK | 12.56934 |
LS_RDATA_A_BISTA | T13 | O | LVCMOS Output | 3.12045 |
BIST_B | T12 | O | LVCMOS Output | 5.63628 |
AMUX_OUT | B20 | O | Analog Test Mux | 9.3849 |
DMUX_OUT | R14 | O | Digital Test Mux | 3.85333 |
DMD_DEN_ARSTZ | T11 | I | ARSTZ | 5.86593 |
TEMP_N | R8 | I | Temp Diode N | 14.63792 |
TEMP_P | R7 | I | Temp Diode P | 15.93219 |
VDD | B7, B13, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18 | P | Digital core supply voltage | Plane |
VDDA | B4, B9, B11, B16, C20, D3, E18, G2, G19 | P | HSSI supply voltage | Plane |
VRESET | B3, R1 | P | Supply voltage for negative bias of micromirror reset signal | Plane |
VBIAS | E1, P1 | P | Supply voltage for positive bias of micromirror reset signal | Plane |
VOFFSET | A20, B2, T1, T20 | P | Supply voltage for HVCMOS logic, stepped up logic level | Plane |
VSS | A17, B6, B10, B14, D18, F3, F19, J3, K2, K19, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19 | G | Ground | Plane |
VSSA | B5, B8, B12, B15, B19, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9 | G | Ground | Plane |
N/C | R15,T14,T15,R16,H18,J18,G18,J19,F18,K20,K18,M19,L20,M18,L18,M20 | No connect |
Parameter Name | Description | MIN | MAX | UNIT |
---|---|---|---|---|
Supply Voltage | ||||
VDD | Supply voltage for LVCMOS core logic and LVCMOS low speed interface (LSIF) (1) | –0.5 | 2.3 | V |
VDDA | Supply voltage for high speed serial interface (HSSI) receivers (1) | –0.3 | 2.2 | V |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode (1)(2) | –0.5 | 11 | V |
VBIAS | Supply voltage for micromirror electrode (1) | –0.5 | 17 | V |
VRESET | Supply voltage for micromirror electrode (1) | –13 | 0.5 | V |
| VDDA – VDD | | Supply voltage delta (absolute value) (3) | 0.3 | V | |
| VBIAS – VOFFSET | | Supply voltage delta (absolute value) (4) | 11 | V | |
| VBIAS – VRESET | | Supply voltage delta (absolute value) (5) | 30 | V | |
Input Voltage | ||||
Input voltage for other inputs – LSIF and LVCMOS (1) | –0.5 | 2.45 | V | |
Input voltage for other inputs – HSSI (1)(6) | –0.2 | VDDA | V | |
Low speed interface (LSIF) | ||||
fCLOCK | LSIF clock frequency (LS_CLK) | 130 | MHz | |
| VID | | LSIF differential input voltage magnitude (6) | 810 | mV | |
IID | LSIF differential input current(7) | 10 | mA | |
High speed serial interface (HSSI) | ||||
fCLOCK | HSSI clock frequency (DCLK) | 1.65 | GHz | |
| VID | | HSSI differential input voltage magnitude Data Lane (6) | 700 | mV | |
| VID | | HSSI differential input voltage magnitude Clock Lane (6) | 700 | mV | |
Environmental | ||||
TARRAY | Temperature, operating(8) | 0 | 90 | °C |
TARRAY | Temperature, non-operating(8) | –40 | 90 | °C |
TDP | Dew point temperature, operating and non-operating (non-condensing) | 81 | ºC |
SYMBOL | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
TDMD | DMD storage temperature | –40 | 80 | ºC |
TDP-AVG | Average dew point temperature (non-condensing) (1) | 28 | ºC | |
TDP-ELR | Elevated dew point temperature range (non-condensing) (2) | 28 | 36 | ºC |
CTELR | Cumulative time in the elevated dew point temperature range | 24 | Months |