DLPS186 Data sheet

DLPS186A March 2021 – May 2022 DLP650TE

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FYP|149
- MCLG039

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)

SYMBOL	PARAMETER ⁽¹⁾⁽²⁾	TEST CONDITIONS ⁽¹⁾	MIN	TYP	MAX	UNIT
Current – Typical
I_DD	Supply current V_DD⁽³⁾			800	1250	mA
I_DDA	Supply current V_DDA⁽³⁾			900	1200	mA
I_DDA	Supply current V_DDA⁽³⁾	single macro mode		500	600	mA
I_OFFSET	Supply current V_OFFSET⁽⁴⁾⁽⁵⁾			23	35	mA
I_BIAS	Supply current V_BIAS⁽⁴⁾⁽⁵⁾			2.4	3.8	mA
I_RESET	Supply current V_RESET⁽⁵⁾		-10.5	-7.7		mA
Power – Typical
P_DD	Supply power dissipation V_DD⁽³⁾			1440	2437.5	mW
P_DDA	Supply power dissipation V_DDA⁽³⁾			1620	2340	mW
P_DDA	Supply power dissipation V_DDA⁽³⁾	single macro mode		900	1170	mW
P_OFFSET	Supply power dissipation V_OFFSET⁽⁴⁾⁽⁵⁾			230	367.5	mW
P_BIAS	Supply power dissipation VBIAS ⁽⁴⁾⁽⁵⁾			38.4	62.7	mW
P_RESET	Supply power dissipation V_RESET⁽⁵⁾			92.4	131.25	mW
P_TOTAL	Supply power dissipation Total			3420.8	5338.95	mW
LVCMOS Input
I_IL	Low level input current ⁽⁶⁾	V_DD = 1.95 V , V_I = 0 V	–100			nA
I_IH	High level input current ⁽⁶⁾	V_DD = 1.95 V , V_I = 1.95 V			135	µA
LVCMOS Output
V_OH	DC output high voltage ⁽⁷⁾	I_OH = -2 mA	0.8 x V_DD			V
V_OL	DC output low voltage ⁽⁷⁾	I_OL = 2 mA			0.2 x V_DD	V
Receiver Eye Characteristics
A1	Minimum data eye opening ⁽⁸⁾		100		600	mV
A1	Minimum clock eye opening ⁽⁸⁾		295		600	mV
A2	Maximum signal swing ⁽⁸⁾⁽⁹⁾				600	mV
X1	Maximum eye closure ⁽⁸⁾				0.275	UI
X2	Maximum eye closure ⁽⁸⁾				0.4	UI
\| t_DRIFT \|	Drift between Clock and Data between Training Patterns				20	ps
Capacitance
C_IN	Input capacitance LVCMOS	f = 1 MHz			10	pF
C_IN	Input capacitance LSIF (low speed interface)	f = 1 MHz			20	pF
C_IN	Input capacitance HSSI (high speed serial interface) - Differential - Clock and Data pins	f = 1 MHz			5	pF
C_OUT	Output capacitance	f = 1 MHz			10	pF

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than specified limit.

(4) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than specified limit.

(5) Supply power dissipation based on 3 global resets in 200 µs.

(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.

(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.

(8) Refer to Figure 6-12 (1e-12 BER).

(9) Defined in Recommended Operation Conditions.