DLPS241 april   2023 DLP670RE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Device Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYE|350
Thermal pad, mechanical data (Package|Pins)

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN MAX UNIT
SUPPLY VOLTAGES
VCC Supply voltage for LVCMOS core logic(1) –0.5 4 V
VCCI Supply voltage for LVDS receivers(1) –0.5 4 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(1)(2) –0.5 9 V
VBIAS Supply voltage for micromirror electrode(1) –0.5 17 V
VRESET Supply voltage for micromirror electrode(1) –11 0.5 V
| VCC – VCCI | Supply voltage change (absolute value)(3) 0.3 V
| VBIAS – VOFFSET | Supply voltage change (absolute value)(4) 8.75 V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins(1) –0.5 VCC + 0.15 V
Input voltage for all other LVDS input pins(1)(5) –0.5 VCCI + 0.15 V
| VID | Input differential voltage (absolute value)(6) 700 mV
IID Input differential current(6) 7 mA
CLOCKS
ƒclock Clock frequency for LVDS interface, DCLK (all channels) 460 MHz
ENVIRONMENTAL
TARRAY and TWINDOW Temperature, operating(7) 0 90 °C
Temperature: non-operating(7) –40 90 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(8) 30 °C
TDP Dew Point temperature, operating and non-operating (non-condensing) 81 °C
(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified voltages.
(3) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
(4) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to Section 9 for additional information.
(5) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors
(7) The highest temperature of the active array (as calculated by Section 7.6) or of any point along the Window Edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, add a test point to that location.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.