The following are recommendations for the power
connections to the DMD or DMD PCB:
- Solid planes are
required for DMD_P3P3V(3.3V), DMD_P1P8V and
Ground.
- TI strongly recommends
partial power planes are used for VOFFSET, VRESET,
and VBIAS.
- VOFFSET, VBIAS, VRESET, VCC,
and VCCI power rails must be kept within the
specified operating range. This includes
effects from ripple and DC error.
- To accommodate power supply
transient current requirements, adequate
decoupling capacitance must be placed as near the
DMD VOFFSET, VBIAS, VRESET, VCC, and VCCI pins as
possible.
- Do not swap DMDs while the
DMD is still powered on (this is called hot
swapping). All DMD power supply rails and signals
must be 0 volts (not driven) before connecting or
disconnecting the DMD physical interface.
- Do not allow power to be
applied to the DMD when one or more signal pins
are not being driven.
- Decoupling capacitor
locations for the DMD must be as close as possible
to the DMD. The pads of the capacitors must be
connected to at least two or three vias to get a
very low impedance to ground as shown in Figure 10-3.
Furthermore, the capacitor must be in the flow of
the power trace as it goes to the input of the
DMD.
- It is extremely important to
adhere to the Section 9.1
and Section 9.2
and do not allow the DMD power-supply levels to be
outside of the recommended operating conditions
specified in the DMD data sheet.
These figures show examples of bypass decoupling capacitor layout.
![Poor Layout GUID-20201114-CA0I-GXXF-GZP3-SPKBZ9WNFTRZ-low.jpg](/ods/images/DLPS194A/GUID-20201114-CA0I-GXXF-GZP3-SPKBZ9WNFTRZ-low.jpg)
Figure 10-2 Poor Layout
Figure 10-3 Good Layout