DLPS242A March   2023  – March 2024 DLP781TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Timing Requirements
    9.     15
    10. 5.8  System Mounting Interface Loads
    11.     17
    12. 5.9  Micromirror Array Physical Characteristics
    13.     19
    14. 5.10 Micromirror Array Optical Characteristics
    15.     21
    16. 5.11 Window Characteristics
    17. 5.12 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Requirements
      2. 7.4.2 DMD Power Supply Power-Up Procedure
      3. 7.4.3 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
        1. 7.5.2.1 Layers
        2. 7.5.2.2 Impedance Requirements
        3. 7.5.2.3 Trace Width, Spacing
          1. 7.5.2.3.1 Voltage Signals
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Device Nomenclature
      2. 8.2.2 Device Markings
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Requirements

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER DESCRIPTION MIN NOM MAX UNIT
SCP
tSCP_DS SCPDI clock setup time (before SCPCLK falling-edge)(1) 800 ns
tSCP_DH SCPDI hold time (after SCPCLK falling-edge)(1) 900 ns
tSCP_NEG_ENZ Time between falling edge of SCPENZ and the rising edge of SCPCLK(1) 1 µs
tSCP_POS_ENZ Time between falling edge of SCPCLK and the rising edge of SCPENZ(1) 1 µs
tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tri-state).(1) 960 ns
tSCP_PW_ENZ SCPENZ inactive pulse width (high-level) 1 1/Fscpclk
tr Rise time (20% to 80%). See (2) 200 ns
tf Fall time (80% to 20%). See (2) 200 ns
LVDS
tR_LVDS Rise time (20% to 80%). See (3) 500 ps
tF_LVDS Fall time (80% to 20%). See (3) 500 ps
tC Clock Cycle Duration for DCLK_C and DCLK_D(4) 2.5 ns
tW Pulse Duration for DCLK_C/D(4) 1.19 ns
tSU_data Setup Time for High-speed data(15:0) before DCLK(4) 350 ps
tSU_sctrl Setup Time for SCTRL before DCLK(4) 330 ps
tH_data Hold time for High-speed data(15:0) after DCLK(4) 150 ps
tH_sctrl Hold Time for SCTRL after DCLK(4) 170 ps
tSKEW_A2B Skew tolerance between Channel B and Channel A(5)(6)(7) -1.25 1.25 ns
tSKEW_C2D Skew tolerance between Channel C and Channel D(5)(8)(10) –1.25 1.25 ns
(1) See Figure 5-3.
(2) See Figure 5-4.
(3) See Figure 5-6.
(4) See Figure 5-7.
(5) See Figure 5-8.
(6) Channel A (Bus A) includes the following LVDS pairs: DCLK_A, SCTRL_A, and D_A.
(7) Channel B (Bus B) includes the following LVDS pairs: DCLK_B, SCTRL_B, and D_B.
(8) Channel C (Bus C) includes the following LVDS pairs: DCLK_C, SCTRL_C, and D_C.
(9) Channel D (Bus D) includes the following LVDS pairs: DCLK_D, SCTRL_D, and D_D.