DLPS242A March   2023  – March 2024 DLP781TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Timing Requirements
    9.     15
    10. 5.8  System Mounting Interface Loads
    11.     17
    12. 5.9  Micromirror Array Physical Characteristics
    13.     19
    14. 5.10 Micromirror Array Optical Characteristics
    15.     21
    16. 5.11 Window Characteristics
    17. 5.12 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 DMD Power Supply Requirements
      2. 7.4.2 DMD Power Supply Power-Up Procedure
      3. 7.4.3 DMD Power Supply Power-Down Procedure
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
        1. 7.5.2.1 Layers
        2. 7.5.2.2 Impedance Requirements
        3. 7.5.2.3 Trace Width, Spacing
          1. 7.5.2.3.1 Voltage Signals
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Device Nomenclature
      2. 8.2.2 Device Markings
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MIN NOM MAX UNIT
VOLTAGE SUPPLY
VDD Supply voltage for LVCMOS core logic(1) 1.65 1.8 1.95 V
VDDI Supply voltage for LVDS Interface(1) 1.65 1.8 1.95 V
VCC2 Micromirror Electrode and HVCMOS voltage(1)(2) 9.5 10 10.5 V
VMBRST Micromirror Bias / Reset Voltage(1) –17 21.5 V
|VDD – VDDI| Supply voltage delta (absolute value)(3) 0 0.3 V
LVCMOS
VIH(DC) Input High Voltage 0.7 × VDD VDD + 0.3 V
VIL(DC) Input Low Voltage –0.3 0.3 × VDD V
VIH(AC) Input High Voltage 0.8 × VDD VDD + 0.3 V
VIL(AC) Input Low Voltage –0.3 0.2 × VDD V
IOH High-level Output Current 2 mA
IOL Low-level Output Current –2 mA
tPWRDNZ PWRDNZ pulse width(4) 10 ns
SCP INTERFACE
FSCPCLK SCP clock frequency 50 500 kHz
SCPCLKDCDIN SCP Clk Input duty cycle 40% 60%
LVDS INTERFACE
FCLOCK Clock frequency for LVDS interface (all channels), DCLK(5) 400 MHz
DCDIN Input CLK Duty Cycle Distortion tolerance 44% 56%
|VID| Input differential voltage (absolute value)(6) 150 300 440 mV
VCM Common mode voltage(6) 1100 1200 1300 mV
VLVDS LVDS voltage(6) 880 1520 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 2 µs
ZIN Internal differential termination resistance 80 100 120 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL
TARRAY Array temperature, long-term operational(7)(8)(9) 10 40 to 70(10) °C
Array temperature, short-term operational, 500 hour max(8)(11) 0 10 °C
TDP -AVG Average dew point average temperature (non–condensing)(12) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(13) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
QAP-ILL Window aperture illumination overfill(14)(15)(16) 17 W/cm2
SOLID STATE ILLUMINATION
ILLUV Illumination power at wavelengths < 410nm(7)(18) 10 mW/cm2
ILLVIS Illumination power at wavelengths ≥ 410nm and ≤ 800nm(17)(18) 40 W/cm2
ILLIR Ilumination power at wavelengths > 800nm(18) 10 mW/cm2
ILLBLU Illumination power at wavelengths ≥ 410nm and ≤ 475nm(17)(18) 12.8 W/cm2
ILLBLU1 Illumination power at wavelengths ≥ 410nm and ≤ 440nm(17)(18) 2 W/cm2
(1) All voltages are referenced to common ground VSS. VDD, VDDI, and VCC2 power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VCC2 supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit. See the DMD Power Supply Requirements. 
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. The PWRDNZ input pin overrides the SCPENZ input pin and tristates the SCPDO output pin.
(5) See LVDS clock timing requirements in Timing Requirements.
(6) See Figure 5-5 for the LVDS waveform requirements.
(7) Simultaneous exposure of the DMD to the maximum Recommend Operating Conditions for temperature and UV illumination reduces device lifetime.
(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in Figure 6-1 using the Micromirror Array Temperature Calculation.
(9) Long-term is defined as the usable life of the device.
(10) Per Figure 5-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-on/Landed-off Duty Cycle for a definition of micromirror landed duty cycle.
(11) Short-term is the total cumulative time over the useful life of the device.
(12) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(13) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of CTELR.
(14) Applies to region defined in Figure 5-2
(15) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view.  The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may cause system performance degradation.
(17) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).