Featuring over 4 million micromirrors, the high resolution DLP9000 and DLP9000X digital micromirror devices (DMDs) are spatial light modulators (SLMs) that modulate the amplitude, direction, and/or phase of incoming light. This advanced light control technology has numerous applications in the industrial, medical, and consumer markets. The streaming nature of the DLP9000X and its DLPC910 controller enable very high speed continuous data streaming for lithographic applications. Both DMDs enable large build sizes and fine resolution for 3D printing applications. The high resolution provides the direct benefit of scanning larger objects for 3D machine vision applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DLP9000 | CLGA (355) | 42.20 mm x 42.20 mm x 7.00 mm |
DLP9000X |
SPACE
Changes from A Revision (October 2015) to B Revision
Changes from * Revision (September 2014) to A Revision
Reliable function and operation of the DLP9000 family requires that each DMD be used in conjunction with its specific digital controller. The DLP9000X must be driven by a single DLPC910 Controller and the DLP9000 must be driven by two DLPC900 Controllers. These dedicated chipsets provide robust, high resolution, high speed system solutions.
PIN (1) | TYPE (I/O/P) |
SIGNAL | DATA RATE (2) |
INTERNAL TERM (3) |
DESCRIPTION | TRACE (mils) (4) |
|
---|---|---|---|---|---|---|---|
NAME | NO. | ||||||
DATA BUS A | |||||||
D_AN(0) | H10 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(1) | G3 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(2) | G9 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(3) | F4 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_AN(4) | F10 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_AN(5) | E3 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_AN(6) | E9 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(7) | D2 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(8) | J5 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_AN(9) | C9 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_AN(10) | F14 | Input | LVDS | DDR | Differential | Data, Negative | 743 |
D_AN(11) | B8 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(12) | G15 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_AN(13) | B14 | Input | LVDS | DDR | Differential | Data, Negative | 740 |
D_AN(14) | H16 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AN(15) | D16 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_AP(0) | H8 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(1) | G5 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_AP(2) | G11 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(3) | F2 | Input | LVDS | DDR | Differential | Data, Positive | 736 |
D_AP(4) | F8 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_AP(5) | E5 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_AP(6) | E11 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(7) | D4 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(8) | J3 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_AP(9) | C11 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(10) | F16 | Input | LVDS | DDR | Differential | Data, Positive | 741 |
D_AP(11) | B10 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(12) | H14 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_AP(13) | B16 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_AP(14) | G17 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_AP(15) | D14 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
DATA BUS B | |||||||
D_BN(0) | AD8 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_BN(1) | AE3 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(2) | AF8 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_BN(3) | AF2 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_BN(4) | AG5 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(5) | AH8 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(6) | AG9 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(7) | AH2 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_BN(8) | AL9 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(9) | AJ11 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_BN(10) | AF14 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_BN(11) | AE11 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(12) | AH16 | Input | LVDS | DDR | Differential | Data, Negative | 740 |
D_BN(13) | AD14 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_BN(14) | AG17 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_BN(15) | AD16 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_BP(0) | AD10 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_BP(1) | AE5 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(2) | AF10 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(3) | AF4 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_BP(4) | AG3 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(5) | AH10 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(6) | AG11 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(7) | AH4 | Input | LVDS | DDR | Differential | Data, Positive | 740 |
D_BP(8) | AL11 | Input | LVDS | DDR | Differential | Data, Positive | 736 |
D_BP(9) | AJ9 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_BP(10) | AF16 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(11) | AE9 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(12) | AH14 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(13) | AE15 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_BP(14) | AG15 | Input | LVDS | DDR | Differential | Data, Positive | 740 |
D_BP(15) | AE17 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
DATA BUS C | |||||||
D_CN(0) | C15 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(1) | E15 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(2) | A17 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_CN(3) | F20 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(4) | B20 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_CN(5) | G21 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(6) | D22 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(7) | E23 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(8) | B26 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_CN(9) | F28 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(10) | C27 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(11) | J29 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(12) | D26 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CN(13) | H26 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_CN(14) | E29 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_CN(15) | G29 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_CP(0) | C17 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_CP(1) | E17 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(2) | A15 | Input | LVDS | DDR | Differential | Data, Positive | 735 |
D_CP(3) | F22 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(4) | B22 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(5) | H20 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(6) | D20 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(7) | E21 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(8) | B28 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_CP(9) | F26 | Input | LVDS | DDR | Differential | Data, Positive | 735 |
D_CP(10) | C29 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(11) | J27 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_CP(12) | D28 | Input | LVDS | DDR | Differential | Data, Positive | 736 |
D_CP(13) | H28 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_CP(14) | E27 | Input | LVDS | DDR | Differential | Data, Positive | 736 |
D_CP(15) | G27 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
DATA BUS D | |||||||
D_DN(0) | AJ15 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(1) | AC27 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(2) | AK16 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_DN(3) | AE29 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_DN(4) | AE21 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(5) | AF20 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_DN(6) | AL15 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(7) | AG29 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_DN(8) | AD22 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_DN(9) | AG21 | Input | LVDS | DDR | Differential | Data, Negative | 738 |
D_DN(10) | AJ23 | Input | LVDS | DDR | Differential | Data, Negative | 736 |
D_DN(11) | AJ29 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(12) | AF28 | Input | LVDS | DDR | Differential | Data, Negative | 737 |
D_DN(13) | AK22 | Input | LVDS | DDR | Differential | Data, Negative | 741 |
D_DN(14) | AD28 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_DN(15) | AK28 | Input | LVDS | DDR | Differential | Data, Negative | 739 |
D_DP(0) | AJ17 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(1) | AC29 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(2) | AK14 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_DP(3) | AE27 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(4) | AD20 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(5) | AF22 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_DP(6) | AL17 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(7) | AG27 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_DP(8) | AE23 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_DP(9) | AG23 | Input | LVDS | DDR | Differential | Data, Positive | 738 |
D_DP(10) | AJ21 | Input | LVDS | DDR | Differential | Data, Positive | 736 |
D_DP(11) | AJ27 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(12) | AF26 | Input | LVDS | DDR | Differential | Data, Positive | 737 |
D_DP(13) | AK20 | Input | LVDS | DDR | Differential | Data, Positive | 740 |
D_DP(14) | AD26 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
D_DP(15) | AK26 | Input | LVDS | DDR | Differential | Data, Positive | 739 |
SERIAL CONTROL | |||||||
SCTRL_AN | D8 | Input | LVDS | DDR | Differential | Serial Control, Negative | 736 |
SCTRL_BN | AK8 | Input | LVDS | DDR | Differential | Serial Control, Negative | 739 |
SCTRL_CN | G23 | Input | LVDS | DDR | Differential | Serial Control, Negative | 737 |
SCTRL_DN | AH28 | Input | LVDS | DDR | Differential | Serial Control, Negative | 739 |
SCTRL_AP | D10 | Input | LVDS | DDR | Differential | Serial Control, Positive | 736 |
SCTRL_BP | AK10 | Input | LVDS | DDR | Differential | Serial Control, Positive | 739 |
SCTRL_CP | H22 | Input | LVDS | DDR | Differential | Serial Control, Positive | 739 |
SCTRL_DP | AH26 | Input | LVDS | DDR | Differential | Serial Control, Positive | 739 |
CLOCKS | |||||||
DCLK_AN | H2 | Input | LVDS | Differential | Clock, Negative | 740 | |
DCLK_BN | AJ5 | Input | LVDS | Differential | Clock, Negative | 740 | |
DCLK_CN | C23 | Input | LVDS | Differential | Clock, Negative | 736 | |
DCLK_DN | AH22 | Input | LVDS | Differential | Clock, Negative | 736 | |
DCLK_AP | H4 | Input | LVDS | Differential | Clock, Positive | 740 | |
DCLK_BP | AJ3 | Input | LVDS | Differential | Clock, Positive | 740 | |
DCLK_CP | C21 | Input | LVDS | Differential | Clock, Positive | 736 | |
DCLK_DP | AH20 | Input | LVDS | Differential | Clock, Positive | 738 | |
SERIAL COMMUNICATIONS PORT (SCP) | |||||||
SCP_DO | AC3 | Output | LVCMOS | SDR | Serial Communications Port Output | ||
SCP_DI | AD2 | Input | LVCMOS | SDR | Pull-Down | Serial Communications Port Data Input | |
SCP_CLK | AE1 | Input | LVCMOS | Pull-Down | Serial Communications Port Clock | ||
SCP_ENZ | AD4 | Input | LVCMOS | Pull-Down | Active-low Serial Communications Port Enable | ||
MICROMIRROR RESET CONTROL | |||||||
RESET_ADDR(0) | H12 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(1) | C5 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(2) | B6 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_ADDR(3) | A19 | Input | LVCMOS | Pull-Down | Reset Driver Address Select | ||
RESET_MODE(0) | J1 | Input | LVCMOS | Pull-Down | Reset Driver Mode Select | ||
RESET_MODE(1) | G1 | Input | LVCMOS | Pull-Down | Reset Driver Mode Select | ||
RESET_SEL(0) | AK4 | Input | LVCMOS | Pull-Down | Reset Driver Level Select | ||
RESET_SEL(1) | AL13 | Input | LVCMOS | Pull-Down | Reset Driver Level Select | ||
RESET_STROBE | H6 | Input | LVCMOS | Pull-Down | Reset Address, Mode, & Level latched on rising-edge | ||
ENABLES AND INTERRUPTS | |||||||
PWRDNZ | B4 | Input | LVCMOS | Active-low Device Reset | |||
RESET_OEZ | AK24 | Input | LVCMOS | Pull-Down | Active-low output enable for DMD reset driver circuits | ||
RESETZ | AL19 | Input | LVCMOS | Pull-Down | Active-low sets Reset circuits in known VOFFSET state | ||
RESET_IRQZ | C3 | Output | LVCMOS | Active-low, output interrupt to ASIC | |||
VOLTAGE REGULATOR MONITORING | |||||||
PG_BIAS | J19 | Input | LVCMOS | Pull-Up | Active-low fault from external VBIAS regulator | ||
PG_OFFSET | A13 | Input | LVCMOS | Pull-Up | Active-low fault from external VOFFSET regulator | ||
PG_RESET | AC19 | Input | LVCMOS | Pull-Up | Active-low fault from external VRESET regulator | ||
EN_BIAS | J15 | Output | LVCMOS | Active-high enable for external VBIAS regulator | |||
EN_OFFSET | H30 | Output | LVCMOS | Active-high enable for external VOFFSET regulator | |||
EN_RESET | J17 | Output | LVCMOS | Active-high enable for external VRESET regulator | |||
LEAVE PIN UNCONNECTED | |||||||
MBRST(0) | L5 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(1) | M28 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(2) | P4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(3) | P30 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(4) | L3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(5) | P28 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(6) | P2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(7) | T28 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(8) | M4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(9) | L29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(10) | T4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(11) | N29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(12) | N3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(13) | L27 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(14) | R3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(15) | V28 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(16) | V4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(17) | R29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(18) | Y4 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(19) | AA27 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(20) | W3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(21) | W27 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(22) | AA3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(23) | W29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(24) | U5 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(25) | U29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(26) | Y2 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(27) | AA29 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(28) | U3 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(29) | Y30 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(30) | AA5 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
MBRST(31) | R27 | Output | Analog | Pull-Down | For proper DMD operation, do not connect | ||
LEAVE PIN UNCONNECTED | |||||||
RESERVED_PFE | J11 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_TM | AC7 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_XI0 | AC25 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_XI1 | AC23 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_XI2 | J23 | Input | LVCMOS | Pull-Down | For proper DMD operation, do not connect | ||
RESERVED_TP0 | AC9 | Input | Analog | For proper DMD operation, do not connect | |||
RESERVED_TP1 | AC11 | Input | Analog | For proper DMD operation, do not connect | |||
RESERVED_TP2 | AC13 | Input | Analog | For proper DMD operation, do not connect | |||
LEAVE PIN UNCONNECTED | |||||||
RESERVED_BA | AC15 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_BB | J13 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_BC | AC21 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_BD | J21 | Output | LVCMOS | For proper DMD operation, do not connect | |||
RESERVED_TS | AC17 | Output | LVCMOS | For proper DMD operation, do not connect | |||
LEAVE PIN UNCONNECTED | |||||||
NO CONNECT | J7 | For proper DMD operation, do not connect | |||||
NO CONNECT | J9 | For proper DMD operation, do not connect | |||||
NO CONNECT | J25 | For proper DMD operation, do not connect |
PIN | TYPE (I/O/P) |
SIGNAL | DESCRIPTION | |
---|---|---|---|---|
NAME (1) | NO. | |||
VBIAS | A3, A9, A5, A11, A7, B2 | Power | Analog | Supply voltage for positive Bias level of Micromirror reset signal. |
VOFFSET | L1, N1, R1 | Power | Analog | Supply voltage for HVCMOS logic. |
U1, W1 | Power | Analog | Supply voltage for stepped high voltage at Micromirror address electrodes. | |
AC1, AA1 | Power | Analog | Supply voltage for Offset level of MBRST(31:0). | |
VRESET | L31, N31, R31, U31, W31, AA31 | Power | Analog | Supply voltage for negative Reset level of Micromirror reset signal. |
VCC | A21, A23, A25, A27, A29, C1, C31, E31, G31, J31, K2, AC31, AE31, AG1, AG31, AJ31, AK2, AK30, AL3, AL5, AL7, AL21, AL23, AL25, AL27 | Power | Analog | Supply voltage for LVCMOS core logic. Supply voltage for normal high level at Micromirror address electrodes. |
VCCI | H18, H24, M6, M26, P6, P26, T6, T26, V6, V26, Y6, Y26, AD6, AD12, AD18, AD24 | Power | Analog | Supply voltage for LVDS receivers. |
VSS | A1, B12, B18, B24, B30, C7, C13, C19, C25, D6, D12, D18, D24, D30, E1, E7, E13, E19, E25, F6, F12, F18, F24, F30, G7, G13, G19, G25, K4, K6, K26, K28, K30, M2, M30, N5, N27, R5, T2, T30, U27, V2, V30, W5, Y28, AB2, AB4, AB6, AB26, AB28, AB30, AC5, AD30, AE7, AE13, AE19, AE25, AF6, AF12, AF18, AF24, AF30, AG7, AG13, AG19, AG25, AH6, AH12, AH18, AH24, AH30, AJ1, AJ7, AJ13, AJ19, AJ25, AK6, AK12, AK18, AL29 | Power | Analog | Device Ground. Common return for all power. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
SUPPLY VOLTAGES | |||||
VCC | Supply voltage for LVCMOS core logic (2) | –0.5 | 4 | V | |
VCCI | Supply voltage for LVDS receivers (2) | –0.5 | 4 | V | |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode (2) (3) | –0.5 | 9 | V | |
VBIAS | Supply voltage for micromirror electrode (2) | –0.5 | 17 | V | |
VRESET | Supply voltage for micromirror electrode (2) | –11 | 0.5 | V | |
| VCC – VCCI | | Supply voltage delta (absolute value) (4) | 0.3 | V | ||
| VBIAS – VOFFSET | | Supply voltage delta (absolute value) (5) | 8.75 | V | ||
INPUT VOLTAGES | |||||
Input voltage for all other LVCMOS input pins (2) | –0.5 | VCC + 0.3 | V | ||
Input voltage for all other LVDS input pins (2) (6) | –0.5 | VCCI + 0.3 | V | ||
| VID | | Input differential voltage (absolute value) (7) | 700 | mV | ||
IID | Input differential current (7) | 7 | mA | ||
CLOCKS | |||||
ƒclock | DLP9000 | Clock frequency for LVDS interface, DCLK_A | 440 | MHz | |
Clock frequency for LVDS interface, DCLK_B | 440 | ||||
Clock frequency for LVDS interface, DCLK_C | 440 | ||||
Clock frequency for LVDS interface, DCLK_D | 440 | ||||
DLP9000X | Clock frequency for LVDS interface, DCLK_A | 500 | |||
Clock frequency for LVDS interface, DCLK_B | 500 | ||||
Clock frequency for LVDS interface, DCLK_C | 500 | ||||
Clock frequency for LVDS interface, DCLK_D | 500 | ||||
ENVIRONMENTAL | |||||
TARRAY | Array temperature: operational (8) (9) | 0 | 90 | ºC | |
Array temperature: non–operational (9) | -40 | 90 | |||
TWINDOW | Window temperature: operational | 0 | 70 | ºC | |
Window temperature: non–operational | -40 | 90 | |||
|TDELTA| | Absolute termperature delta between the window test points and the ceramic test point TP1(10) | 10 | ºC | ||
RH | Relative Humidity, operating and non–operating | 95% |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
TDMD | DMD storage temperature | -40 | 80 | °C | |
RH | Relative Humidity, (non-condensing) | 95% |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLY VOLTAGES (1) (2) | ||||||
VCC | DLP9000 | Supply voltage for LVCMOS core logic | 3.0 | 3.3 | 3.6 | V |
DLP9000X | Supply voltage for LVCMOS core logic | 3.3 | 3.45 | 3.6 | ||
VCCI | DLP9000 | Supply voltage for LVDS receivers | 3.0 | 3.3 | 3.6 | V |
DLP9000X | Supply voltage for LVDS receivers | 3.3 | 3.45 | 3.6 | ||
VOFFSET | Supply voltage for HVCMOS and micromirror electrodes (3) | 8.25 | 8.5 | 8.75 | V | |
VBIAS | Supply voltage for micromirror electrodes | 15.5 | 16 | 16.5 | V | |
VRESET | –9.5 | –10 | –10.5 | V | ||
|VCCI–VCC| | Supply voltage delta (absolute value) (4) | 0.3 | V | |||
|VBIAS–VOFFSET| | Supply voltage delta (absolute value) (5) | 8.75 | V | |||
LVCMOS PINS | ||||||
VIH | High level Input voltage (6) | 1.7 | 2.5 | VCC + 0.3 | V | |
VIL | Low level Input voltage (6) | – 0.3 | 0.7 | V | ||
IOH | High level output current at VOH = 2.4 V | –20 | mA | |||
IOL | Low level output current at VOL = 0.4 V | 15 | mA | |||
TPWRDNZ | PWRDNZ pulse width (7) | 10 | ns | |||
SCP INTERFACE | ||||||
ƒclock | SCP clock frequency (8) | 500 | kHz | |||
tSCP_SKEW | Time between valid SCPDI and rising edge of SCPCLK (17) | –800 | 800 | ns | ||
tSCP_DELAY | Time between valid SCPDO and rising edge of SCPCLK (17) | 700 | ns | |||
tSCP_BYTE_INTERVAL | Time between consecutive bytes | 1 | µs | |||
tSCP_NEG_ENZ | Time between falling edge of SCPENZ and the first rising edge of SCPCLK | 30 | ns | |||
tSCP_PW_ENZ | SCPENZ inactive pulse width (high level) | 1 | µs | |||
tSCP_OUT_EN | Time required for SCP output buffer to recover after SCPENZ (from tri-state) | 1.5 | ns | |||
ƒclock | SCP circuit clock oscillator frequency (9) | 9.6 | 11.1 | MHz | ||
LVDS INTERFACE | ||||||
ƒclock | DLP9000 | Clock frequency DCLK | 400 | MHz | ||
DLP9000X | Clock frequency DCLK (10) | 400 | 480 | |||
|VID| | Input differential voltage (absolute value) (18) | 100 | 400 | 600 | mV | |
VCM | Common mode (18) | 1200 | mV | |||
VLVDS | LVDS voltage (18) | 0 | 2000 | mV | ||
tLVDS_RSTZ | Time required for LVDS receivers to recover from PWRDNZ | 10 | ns | |||
ZIN | Internal differential termination resistance | 95 | 105 | Ω | ||
ZLINE | Line differential impedance (PWB/trace) | 90 | 100 | 110 | Ω | |
ENVIRONMENTAL (11) For Illumination Source Between 420 nm and 700 nm | ||||||
TARRAY | DLP9000 | Array temperature, Long–term operational (13) (12)(19) | 10 | 40 to 65 (14) | °C | |
Array temperature, Short–term operational (13) (12)(20) | 0 | 10 | ||||
DLP9000X | Array temperature, Long–term operational (13) (12)(19) | 10 | 40 (21) | |||
Array temperature, Short–term operational (13) (12)(20) | 0 | 10 | ||||
TWINDOW | DLP9000 | Window Temperature test points TP2 and TP3, Long-term operational(19) | 10 | 70 | °C | |
DLP9000X | Window Temperature test points TP2 and TP3, Long-term operational(19) | 10 | 40 | |||
|TDELTA| | Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1(15) | 10 | °C | |||
ILLVIS | Illumination | Thermally Limited (16) | mW/cm2 | |||
RH | Relative Humidity (non-condensing) | 95% | ||||
ENVIRONMENTAL (11) For Illumination Source Between 400 nm and 420 nm | ||||||
TARRAY | Array temperature, Long–term operational (13) (12)(19) | 20 | 30 | °C | ||
Array temperature, Short–term operational (13) (12)(20) | 0 | 20 | ||||
TWINDOW | Window Temperature test points TP2 and TP3, Long-term operational(19) | 30 | °C | |||
|TDELTA| | Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1(15) | 10 | °C | |||
ILLVIS | Illumination | 10 | W/cm2 | |||
RH | Relative Humidity (non-condensing) | 95% | ||||
ENVIRONMENTAL (11) For Illumination Source <400 nm and >700 nm | ||||||
TARRAY | DLP9000 | Array temperature, Long–term operational (13) (12)(19) | 10 | 40 to 65 (14) | °C | |
Array temperature, Short–term operational (13) (12)(20) | 0 | 10 | ||||
DLP9000X | Array temperature, Long–term operational (13) (12)(19) | 10 | 40 (21) | |||
Array temperature, Short–term operational (13) (12)(20) | 0 | 10 | ||||
TWINDOW | DLP9000 | Window Temperature test points TP2 and TP3, Long-term operational(19) | 10 | 70 | °C | |
DLP9000X | Window Temperature test points TP2 and TP3, Long-term operational(19) | 10 | 40 | |||
|TDELTA| | Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1(15) | 10 | °C | |||
ILLUV | Illumination, wavelength < 400 nm | 0.68 | mW/cm2 | |||
ILLIR | Illumination, wavelength > 700 nm | 10 | mW/cm2 | |||
RH | Relative Humidity (non-condensing) | 95% |
THERMAL METRIC (1) | DLP9000 | UNIT | ||
---|---|---|---|---|
FLS (CLGA) | ||||
355 PINS | ||||
RθJA | Thermal resistance, active area to test point 1 (TP1) (max) | 0.5 | °C/W |
PARAMETER | TEST CONDITIONS (1) | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | VCC = 3 V, IOH = –20 mA | 2.4 | V | ||
VOL | Low level output voltage | VCC = 3.6, IOL = 15 mA | 0.4 | V | ||
IIH | High–level input current (2) (3) | VCC = 3.6 V, VI = VCC | 250 | µA | ||
IlL | Low level input current | VCC = 3.6 V, VI = 0 | –250 | µA | ||
IOZ | High–impedance output current | VCC = 3.6 V | 10 | µA | ||
CURRENT | ||||||
ICC | Supply current (4) | DLP9000 VCC = 3.6 V, DCLK=400 MHz | 1600 | mA | ||
DLP9000X VCC = 3.6V, DCLK=480 MHz | 1850 | |||||
ICCI | DLP9000 VCCI = 3.6 V, DCLK=400 MHz | 985 | ||||
DLP9000X VCCI = 3.6, DCLK=480 MHz | 1100 | |||||
IOFFSET | Supply current (5) | VOFFSET = 8.75 V | 25 | mA | ||
IBIAS | VBIAS = 16.5 V | 14 | ||||
IRESET | Supply current | VRESET = –10.5 V | 11 | mA | ||
ITOTAL | DLP9000 Total Sum | 2634 | ||||
DLP9000X Total Sum | 3000 | |||||
POWER | ||||||
PCC | Supply power dissipation | DLP9000 VCC = 3.6 V | 5760 | mW | ||
DLP9000X VCC = 3.6 V | 6660 | |||||
PCCI | DLP9000 VCCI = 3.6 V | 3546 | mW | |||
DLP9000X VCCI = 3.6 V | 3960 | |||||
POFFSET | VOFFSET = 8.75 V | 219 | mW | |||
PBIAS | VBIAS = 16.5 V | 231 | mW | |||
PRESET | VRESET = –10.5 V | 115 | mW | |||
PTOTAL | Supply power dissipation (6) | DLP9000 Total Sum, DCLK = 400 MHz | 9871 | mW | ||
DLP9000X Total Sum, DCLK = 480 MHz | 11185 | |||||
CAPACITANCE | ||||||
CI | Input capacitance | ƒ = 1 MHz | 10 | pF | ||
CO | Output capacitance | ƒ = 1 MHz | 10 | pF | ||
Reset group capacitance MBRST(31:0) | ƒ = 1 MHz; 2560 × 50 micromirrors | 230 | 290 | pF |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
SCP INTERFACE (2) | |||||||
tr | Rise time | 20% to 80% | 200 | ns | |||
tƒ | Fall time | 80% to 20% | 200 | ns | |||
LVDS INTERFACE (2) | |||||||
tr | Rise time | 20% to 80% | 100 | 400 | ps | ||
tƒ | Fall time | 80% to 20% | 100 | 400 | ps | ||
LVDS CLOCKS (3) | |||||||
tc | Cycle time | DLP9000 | DCLK_A, 50% to 50% | 2.5 | ns | ||
DCLK_B, 50% to 50% | 2.5 | ||||||
DCLK_C, 50% to 50% | 2.5 | ||||||
DCLK_D, 50% to 50% | 2.5 | ||||||
DLP9000X | DCLK_A, 50% to 50% | 2.083 | |||||
DCLK_B, 50% to 50% | 2.083 | ||||||
DCLK_C, 50% to 50% | 2.083 | ||||||
DCLK_D, 50% to 50% | 2.083 | ||||||
tw | Pulse duration | DLP9000 | DCLK_A, 50% to 50% | 1.19 | 1.25 | ns | |
DCLK_B, 50% to 50% | 1.19 | 1.25 | |||||
DCLK_C, 50% to 50% | 1.19 | 1.25 | |||||
DCLK_D, 50% to 50% | 1.19 | 1.25 | |||||
DLP9000X | DCLK_A, 50% to 50% | 1.031 | 1.042 | ||||
DCLK_B, 50% to 50% | 1.031 | 1.042 | |||||
DCLK_C, 50% to 50% | 1.031 | 1.042 | |||||
DCLK_D, 50% to 50% | 1.031 | 1.042 | |||||
LVDS INTERFACE (3) | |||||||
tsu | Setup time | D_A(15:0) before rising or falling edge of DCLK_A | 0.2 | ns | |||
D_B(15:0) before rising or falling edge of DCLK_B | 0.2 | ||||||
D_C(15:0) before rising or falling edge of DCLK_C | 0.2 | ||||||
D_D(15:0) before rising or falling edge of DCLK_D | 0.2 | ||||||
tsu | Setup time | SCTRL_A before rising or falling edge of DCLK_A | 0.2 | ns | |||
SCTRL_B before rising or falling edge of DCLK_B | 0.2 | ||||||
SCTRL_C before rising or falling edge of DCLK_C | 0.2 | ||||||
SCTRL_D before rising or falling edge of DCLK_D | 0.2 | ||||||
th | Hold time | DLP9000 | D_A(15:0) after rising or falling edge of DCLK_A | 0.5 | ns | ||
D_B(15:0) after rising or falling edge of DCLK_B | 0.5 | ||||||
D_C(15:0) after rising or falling edge of DCLK_C | 0.5 | ||||||
D_D(15:0) after rising or falling edge of DCLK_D | 0.5 | ||||||
DLP9000X | D_A(15:0) after rising or falling edge of DCLK_A | 0.4 | |||||
D_B(15:0) after rising or falling edge of DCLK_B | 0.4 | ||||||
D_C(15:0) after rising or falling edge of DCLK_C | 0.4 | ||||||
D_D(15:0) after rising or falling edge of DCLK_D | 0.4 | ||||||
th | Hold time | DLP9000 | SCTRL_A after rising or falling edge of DCLK_A | 0.5 | ns | ||
SCTRL_B after rising or falling edge of DCLK_B | 0.5 | ||||||
SCTRL_C after rising or falling edge of DCLK_C | 0.5 | ||||||
SCTRL_D after rising or falling edge of DCLK_D | 0.5 | ||||||
DLP9000X | SCTRL_A after rising or falling edge of DCLK_A | 0.4 | |||||
SCTRL_B after rising or falling edge of DCLK_B | 0.4 | ||||||
SCTRL_C after rising or falling edge of DCLK_C | 0.4 | ||||||
SCTRL_D after rising or falling edge of DCLK_D | 0.4 | ||||||
LVDS INTERFACE (3) | |||||||
tskew | Skew time | Channel B relative to Channel A | DLP9000 Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0) |
–1.25 | 1.25 | ns | |
DLP9000 Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0) |
|||||||
DLP9000X Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0) |
-1.04 | 1.04 | ns | ||||
DLP9000X Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0) |
|||||||
Channel D relative to Channel C | DLP9000 Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0) |
–1.25 | 1.25 | ns | |||
DLP9000 Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0) |
|||||||
DLP9000X Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0) |
-1.04 | 1.04 | ns | ||||
DLP9000X Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0) |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
CI | Input capacitance | ƒ = 1 MHz | 10 | pF | |
CO | Output capacitance | ƒ = 1 MHz | 10 | pF | |
CIM | MBRST(31:0) input capacitance | f = 1 MHz. All inputs interconnected. | 230 | 290 | pF |
When the DLP9000 DMD is controlled by two DLPC900 controllers, these digital controllers offer four modes of operation.
In video mode, the video source is displayed on the DMD at the rate of the incoming video source.
In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1.
When the DLP9000X DMD is controlled by the DLPC910 controller, the digital controller offers streaming 1-bit binary patterns to the DMD at speeds greater than 61 Gigabits per second (Gbps). The patterns are streamed from a customer designed applications processor into the DLPC910 input LVDS data interface. Table 2 shows the pattern rates for the different DMD Reset Modes.
BIT DEPTH | VIDEO PATTERN MODE (Hz) | PRE-STORED or PATTERN ON-THE-FLY MODE (Hz) |
---|---|---|
1 | 2880 | 9523 |
2 | 1440 | 3289 |
3 | 960 | 2638 |
4 | 720 | 1364 |
5 | 480 | 823 |
6 | 480 | 672 |
7 | 360 | 500 |
8 | 247 | 247 |
RESET MODE(1) | MAX PIXEL DATA RATE (Gbps)(2) | MAX PATTERN RATE (Hz) (5) |
---|---|---|
Global | 53.42 | 13043(3) |
Single | 56.46 | 13783 (4) |
Dual | 59.89 | 14624 (4) |
Quad | 61.39 | 14989(4) |
PARAMETER | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
Maximum system mounting interface load to be applied to the: | Thermal interface area (See Figure 8) | 35 | lbs | |||
Electrical interface area | 300 | lbs | ||||
Datum A interface area (1) | 160 | lbs |
VALUE | UNIT | ||||
---|---|---|---|---|---|
M | Number of active columns | See Figure 9 | 2560 | micromirrors | |
N | Number of active rows | 1600 | micromirrors | ||
P | Micromirror (pixel) pitch | 7.56 | µm | ||
Micromirror active array width | M × P | 19.3536 | mm | ||
Micromirror active array height | N × P | 12.096 | mm | ||
Micromirror active border | Pond of micromirror (POM) (1) | 14 | micromirrors/ side | ||
Micromirror total area | P2 x M x N (converted to cm) | 2.341 | cm2 |
Refer to Optical Interface and System Image Quality for important information.
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
α | Micromirror tilt angle | DMD landed state (1) | 12 | ° | ||
β | Micromirror tilt angle tolerance (1) (2) (3) (4) (5) | –1 | 1 | ° | ||
Micromirror tilt direction (5) (6) | See Figure 11 | 44 | 45 | 46 | ° | |
Number of out-of-specification micromirrors (7) | Adjacent micromirrors | 0 | micromirrors | |||
Non-adjacent micromirrors | 10 | |||||
Micromirror crossover time (8) (9) | Typical performance | 2.5 | μs | |||
DMD efficiency within the wavelength range 400 nm to 420 nm (10) | 68% | |||||
DMD photopic efficiency within the wavelength range 420 nm to 700 nm (10) | 66% |
Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in a) through c) below:
NOTE
TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED ABOVE.
PARAMETER (1) | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Window material designation | Corning 7056 | ||||
Window refractive index | at wavelength 589 nm | 1.487 | |||
Window aperture | See (2) | ||||
Illumination overfill | Refer to Illumination Overfill | ||||
Window transmittance, single–pass through both surfaces and glass (3) | At wavelength 405 nm. Applies to 0° and 24° AOI only. | 95% | |||
Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI. | 97% | ||||
Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI. | 97% |
The DMD is a component of one or more DLP® chipsets. Reliable function and operation of the DMD requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DMD.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 12 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation section.
The DMD is a 0.9 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 9.
The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).
The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram.
The positive or negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror Array Optical Characteristics. The micromirrors are electrically tied to the micromirror reset signals (MBRST) and the micromirror array is divided into reset groups.
Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative (–) tilt angle state corresponds to an 'off' pixel.
Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration and Functions for more information on micromirror reset control.
The DMD consists of 4096000 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional orthogonal pixel array. Refer to Figure 9 and Figure 13.
Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to Micromirror Array Optical Characteristics and Figure 14.
The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package, as shown in Figure 13.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update.
Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a – α position.
Updating the angular position of the micromirror array consists of two steps. First, update the contents of the CMOS memory. Second, apply a micromirror reset (also referred as Mirror Clocking Pulse) to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror reset pulses are generated internally by the DMD, with application of the pulses being coordinated by the DLPC900 or the DLPC910 digital controller.
For more information, refer to the TI application report DLPA008, DMD101: Introduction to Digital Micromirror Device (DMD) Technology.
The DLP9000 DMD is controlled by two DLPC900 digital controllers. The digital controller operates in two different modes. The first is video mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are downloaded over USB or pre-stored in flash memory, and then streamed to the DMD. The resulting DMD pattern rate depends on which mode and bit-depth is selected. For more information, refer to the DLPC900 data sheet listed under Related Documentation.
The DLP9000X DMD is controlled by one DLPC910 digital controller. The digital controller offers high speed streaming mode where 1-bit binary patterns are accepted at the LVDS interface input, and then streamed to the DMD. To ensure reliable operation, the DLP9000X must always be used with the DLPC910. For more information, refer to the DLPC910 data sheet listed under Related Documentation.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously.
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections.
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.
Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations:
Where:
TARRAY = Computed micromirror array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 15
RARRAY–TO–CERAMIC = DMD package thermal resistance from micromirror array to outside ceramic (°C/W) specified in Thermal Information
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W)
QELECTRICAL = DMD electrical power dissipation (W), specified in Electrical Characteristics
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
SL = Measured ANSI screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. Absorbed optical power from the illumination source is variable and depends on the operating state of the micromirrors and the intensity of the light source. Equations shown above produce a total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00274 W/lm.
Sample Calculation for typical projection application:
TCERAMIC = 55°C, assumed system measurement; refer to Recommended Operating Conditions regarding specific limits.
SL = 2000 lm
QELECTRICAL = 9.87W for the DLP9000 (refer to the power specifications in Electrical Characteristics)
CL2W = 0.00274 W/lm
QARRAY = 9.87 W + (0.00274 W/lm × 2000 lm) = 15.35 W
TARRAY = 55°C + (15.35 W × 0.5 ºC/W) = 62.68°C
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages) always add to 100.
Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.
Individual DMD mirror duty cycles vary by application as well as the mirror location on the DMD within any specific application. DMD mirror useful life are maximized when every individual mirror within a DMD approaches 50/50 (or 1/1) duty cycle. Therefore, for the DLPC900 and DLP9000 chipset, it is recommended that DMD Idle Mode be enabled as often as possible. Examples are whenever the system is idle, the illumination is disabled, between sequential pattern exposures (if possible), or when the exposure pattern sequence is stopped for any reason. This software mode provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states. Refer to the DLPC900 Programmer’s Guide DLPU018 for a description of the DMD Idle Mode command. For the DLPC910 and DLP9000X chipset, it is recommended the controlling applications processor provide a 50/50 pattern sequence to the DLPC910 for display on the DLP9000X as often as possible, similar to the above examples stated for the DLPC900. The pattern provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states.
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life. This is quantified in the de-rating curve shown in Figure 16. The importance of this curve is that:
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle.
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 3.
GRAYSCALE VALUE | LANDED DUTY CYCLE |
---|---|
0% | 0/100 |
10% | 10/90 |
20% | 20/80 |
30% | 30/70 |
40% | 40/60 |
50% | 50/50 |
60% | 60/40 |
70% | 70/30 |
80% | 80/20 |
90% | 90/10 |
100% | 100/0 |
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% × Blue_Scale_Value)
Where:
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red, Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green, blue color intensities would be as shown in Table 4.
RED CYCLE PERCENTAGE 50% |
GREEN CYCLE PERCENTAGE 20% |
BLUE CYCLE PERCENTAGE 30% |
LANDED DUTY CYCLE |
---|---|---|---|
RED SCALE VALUE | GREEN SCALE VALUE | BLUE SCALE VALUE | |
0% | 0% | 0% | 0/100 |
100% | 0% | 0% | 50/50 |
0% | 100% | 0% | 20/80 |
0% | 0% | 100% | 30/70 |
12% | 0% | 0% | 6/94 |
0% | 35% | 0% | 7/93 |
0% | 0% | 60% | 18/82 |
100% | 100% | 0% | 70/30 |
0% | 100% | 100% | 50/50 |
100% | 0% | 100% | 80/20 |
12% | 35% | 0% | 13/87 |
0% | 35% | 60% | 25/75 |
12% | 0% | 60% | 24/76 |
100% | 100% | 100% | 100/0 |