DLPS033D
november 2014 – july 2023
DLP9500UV
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Storage Conditions
7.3
ESD Ratings
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
Electrical Characteristics
7.7
LVDS Timing Requirements
7.8
LVDS Waveform Requirements
7.9
Serial Control Bus Timing Requirements
7.10
Systems Mounting Interface Loads
7.11
Micromirror Array Physical Characteristics
7.12
Micromirror Array Optical Characteristics
7.13
Chipset Component Usage Specification
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
8.3.2
DLPA200 - DMD Micromirror Drivers
8.3.3
DLPR410 - PROM for DLP Discovery 4100 Chipset
8.3.4
DLP9500 - DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
8.3.4.1
DLP9500UV 1080p Chipset Interfaces
8.3.4.1.1
DLPC410 Interface Description
8.3.4.1.1.1
DLPC410 IO
8.3.4.1.1.2
Initialization
8.3.4.1.1.3
DMD Device Detection
8.3.4.1.1.4
Power Down
8.3.4.1.2
DLPC410 to DMD Interface
8.3.4.1.2.1
DLPC410 to DMD IO Description
8.3.4.1.2.2
Data Flow
8.3.4.1.3
DLPC410 to DLPA200 Interface
8.3.4.1.3.1
DLPA200 Operation
8.3.4.1.3.2
DLPC410 to DLPA200 IO Description
8.3.4.1.4
DLPA200 to DLP9500UV Interface
8.3.4.1.4.1
DLPA200 to DLP9500UV Interface Overview
8.3.5
Measurement Conditions
8.4
Device Functional Modes
8.4.1
Single Block Mode
8.4.2
Dual Block Mode
8.4.3
Quad Block Mode
8.4.4
Global Block Mode
8.5
Window Characteristics and Optics
8.5.1
Optical Interface and System Image Quality
8.5.2
Numerical Aperture and Stray Light Control
8.5.3
Pupil Match
8.5.4
Illumination Overfill
8.6
Micromirror Array Temperature Calculation
8.6.1
Package Thermal Resistance
8.6.2
Case Temperature
8.6.3
Micromirror Array Temperature Calculation
8.7
Micromirror Landed-On and Landed-Off Duty Cycle
8.7.1
Definition of Micromirror Landed-On/Landed-Off Duty Cycle
8.7.2
Landed Duty Cycle and Useful Life of the DMD
8.7.3
Landed Duty Cycle and Operational DMD Temperature
8.7.4
Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
9
Application and Implementation
9.1
Application Information
9.1.1
DMD Reflectivity Characteristics
9.1.1.1
Design Considerations Influencing DMD Reflectivity
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Device Description
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.3.1
Power-Up Sequence (Handled by the DLPC410)
9.3.2
DMD Power-Up and Power-Down Procedures
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Impedance Requirements
9.4.1.2
PCB Signal Routing
9.4.1.3
Fiducials
9.4.1.4
PCB Layout Guidelines
9.4.1.4.1
DMD Interface
9.4.1.4.1.1
Trace Length Matching
9.4.1.4.2
DLP9500UV Decoupling
9.4.1.4.2.1
Decoupling Capacitors
9.4.1.4.3
VCC and VCC2
9.4.1.4.4
DMD Layout
9.4.1.4.5
DLPA200
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
Device Nomenclature
10.1.2
Device Marking
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Related Links
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
FLN|355
MCLG019B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
dlps033d_oa