DLPS015G april   2010  – june 2023 DLPA200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Configurations Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics Control Logic
    6. 7.6  5-V Linear Regulator
    7. 7.7  Bias Voltage Boost Converter
    8. 7.8  Reset Voltage Buck-Boost Converter
    9. 7.9  VOFFSET/DMDVCC2 Regulator
    10. 7.10 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Linear Regulator
      2. 8.3.2 Bias Voltage Boost Converter
      3. 8.3.3 Reset Voltage Buck-Boost Converter
      4. 8.3.4 VOFFSET/DMDVCC2 Regulator
      5. 8.3.5 Serial Communications Port (SCP)
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Component Selection Guidelines
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Rail Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding Guidelines
    2. 11.2 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Serial Communications Port (SCP)

The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the primary ASIC or FPGA, and one or more secondary DLPA200s (and/or other DLP devices).

Table 8-1 Serial Communications Port Signal Definitions
SIGNALI/OFROM/TOTYPEDESCRIPTION
SCPCKISCP bus primary to secondaryLVTTL compatibleSCP bus serial transfer clock. The host processor (primary) generates this clock.
SCPENISCP bus primary to secondaryLVTTL compatibleSCP bus access enable (low true). When high, secondary will reset to idle state, and SCPDO output will tri-state. Pulling SCPEN low initiates a read or write access. SCPEN must remain low for an entire read/write access, and must be pulled high after the last data cycle. To abort a read or write cycle, pull SCPEN high at any point.
SCPDIISCP bus primary to secondaryLVTTL compatibleSCP bus serial data input. Data bits are valid and must be clocked in on the falling edge of SCPCK.
SCPDOOSCP bus secondary to primaryLVTTL, open drain w/tri-stateSCP bus serial data output. Data bits must clocked out on the rising edge of SCPCK. A 1-kΩ pullup resistor to the 3.3 volt ASIC supply is required.
IRQOSCP bus secondary to primaryLVTTL, open drainNot part of the SCP bus definition. Asynchronous interrupt signal from secondary to request service from primary. A 1-kΩ pullup resistor to the 3.3-V ASIC supply is required.