DLPS043B June   2014  – February 2018 DLPA2000

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Motor Driver Timing Requirements
    8. 6.8 Data Transmission Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DMD Regulators
      2. 7.3.2  RGB Strobe Decoder
      3. 7.3.3  LED Current Control
      4. 7.3.4  Calculating Inductor Peak Current
      5. 7.3.5  LED Current Accuracy
      6. 7.3.6  Transient Current Limiting
      7. 7.3.7  1.1-V Regulator (Buck Converter)
      8. 7.3.8  Motor Driver
        1. 7.3.8.1 Motor Driver Overcurrent Protection
      9. 7.3.9  Measurement System
      10. 7.3.10 Protection Circuits
        1. 7.3.10.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
        2. 7.3.10.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
        3. 7.3.10.3 DMD Regulator Fault (DMD_FLT)
        4. 7.3.10.4 V6V Power-Good (V6V_PGF) Fault
        5. 7.3.10.5 VLED Overvoltage (VLED_OVP) Fault
        6. 7.3.10.6 VLED Power Save Mode
        7. 7.3.10.7 V1V8 PG Failure
        8. 7.3.10.8 Interrupt Pin (INTZ)
        9. 7.3.10.9 SPI
      11. 7.3.11 Password Protected Registers
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. Table 7. Register Description
      2. 7.5.1     Chip Revision Register
        1. Table 8. Chip Revision Register Field Descriptions
      3. 7.5.2     Enable Register
        1. Table 9. Enable Register Field Descriptions
      4. 7.5.3     Transient-Current Limit Settings
        1. Table 10. Transient-Current Limit Settings Field Descriptions
      5. 7.5.4     Regulation Current MSB, SW4
        1. Table 11. Regulation Current MSB, SW4 Field Descriptions
      6. 7.5.5     Regulation Current LSB, SW4
        1. Table 12. Regulation Current LSB, SW4 Field Descriptions
        2. Table 13. Regulation Current LSB, SW4 Bit Definitions
      7. 7.5.6     Regulation Current MSB, SW5
        1. Table 14. Regulation Current MSB, SW5 Field Descriptions
      8. 7.5.7     Regulation Current LSB, SW5
        1. Table 15. Regulation Current LSB, SW5 Field Descriptions
        2. Table 16. Regulation Current LSB, SW5 Bit Definitions
      9. 7.5.8     Regulation Current MSB, SW6
        1. Table 17. Regulation Current MSB, SW6 Field Descriptions
      10. 7.5.9     Regulation Current LSB, SW6
        1. Table 18. Regulation Current LSB, SW6 Field Descriptions
        2. Table 19. Regulation Current LSB, SW6 Bit Definitions
      11. 7.5.10    Switch On/Off Control (Direct Mode)
        1. Table 20. Switch On/Off Control (Direct Mode) Field Descriptions
      12. 7.5.11    AFE (MUX) Control
        1. Table 21. AFE (MUX) Control Field Descriptions
      13. 7.5.12    Break Before Make (BBM) Timing
        1. Table 22. BBM Timing Field Descriptions
      14. 7.5.13    Interrupt Register
        1. Table 23. Interrupt Register Field Descriptions
      15. 7.5.14    Interrupt Mask Register
        1. Table 24. Interrupt Mask Register Field Descriptions
      16. 7.5.15    Timing Register VOFS, VBIAS, VRST, and RESETZ
        1. Table 25. Timing Register VOFS, VBIAS, VRST, and RESETZ Field Descriptions
        2. Table 26. Timing Register VOFS, VBIAS, VRST, and RESETZ Bit Definitions
      17. 7.5.16    Motor Control Register
        1. Table 27. Motor Control Register Field Descriptions
      18. 7.5.17    Password Register
        1. Table 28. Password Register Field Descriptions
      19. 7.5.18    System Configuration Register
        1. Table 29. System Configuration Register Field Descriptions
      20. 7.5.19    User EEPROM, BYTE0
        1. Table 30. User EEPROM, BYTE0 Field Descriptions
      21. 7.5.20    User EEPROM, BYTE1
        1. Table 31. User EEPROM, BYTE1 Field Descriptions
      22. 7.5.21    User EEPROM, BYTE2
        1. Table 32. User EEPROM, BYTE2 Field Descriptions
      23. 7.5.22    User EEPROM, BYTE3
        1. Table 33. User EEPROM, BYTE3 Field Descriptions
      24. 7.5.23    User EEPROM, BYTE4
        1. Table 34. User EEPROM, BYTE4 Field Descriptions
      25. 7.5.24    User EEPROM, BYTE5
        1. Table 35. User EEPROM, BYTE5 Field Descriptions
      26. 7.5.25    User EEPROM, BYTE6
        1. Table 36. User EEPROM, BYTE6 Field Descriptions
      27. 7.5.26    User EEPROM, BYTE7
        1. Table 37. User EEPROM, BYTE7 Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Projector Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Typical Mobile Sensing Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Dlpc150 System Interfaces
          1. 8.3.2.1.1 Control Interface
      3. 8.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (see (1)(2))
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLIES
INPUT VOLTAGE
VI Input voltage range VINA, VINR, VINL, VINC 2.7 3.6 6 V
Extended input voltage range(1) 2.3 3.6 6
VLOW_BAT Low-battery warning threshold VINA falling 3 V
Hysteresis VINA rising 100 mV
Vhys(UVLO) Undervoltage lockout threshold VINA falling (through 5-bit trim function) 2.3 4.5 V
Hysteresis VINA rising 100 mV
VSTARTUP Startup voltage VBIAS, VOFS, VRST; loaded with 2 mA 2.5 V
INPUT CURRENT
IQ ACTIVE mode Motor current excluded 15 mA
ISTD STANDBY mode 900 µA
IIDLE IDLE mode 10 µA
INTERNAL SUPPLIES
VV6V Internal supply, analog 6.25 V
CLDO_V6V Filter capacitor for V6V LDO 100 nF
VV2V5 Internal supply, logic 2.5 V
CLDO_V2V5 Filter capacitor for V2V5 LDO 2.2 µF
DMD REGULATOR
RDS(ON) MOSFET ON-resistance Switch E (from VINR to SWN) 1000 mΩ
Switch F (from SWP to PGNDR) 320
VFW Forward voltage drop Switch G(2) (from SWP to VBIAS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA		 1.3 V
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA		 1.3
tDIS Rail discharge time VIN = 2.9 V; COUT = 110 nF 40 µs
tPG Power-good timeout Not tested in production 6 ms
ILIMIT Switch current limit 312 mA
L Inductor value 10 µH
VOFS REGULATOR
VOFS Output voltage 10 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT = 0 to 2 mA –19 V/A
DC line regulation VINA, VINL, VINR, VINC 2.7 to 6.0 V, IOUT = 2 mA 35 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF(3) 375 mVpp
IOUT Output current 0 3 mA
PG Power-good threshold
(fraction of nominal output voltage)		 VOFS rising 86%
VOFS falling 66%
RDIS Output discharge resistor Active when rail is disabled 100 Ω
COUT Output capacitor Recommended value (output capacitors for VOFS/VBIAS must be equal) 110 220 nF
tDISCHARGE < 40 µs at 2.9 V 100 110 nF
VBIAS REGULATOR
VBIAS Output voltage 18 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT = 0 to 2 mA –14 V/A
DC line regulation VINA, VINL, VINR, VINC 2.7 to 6 V,
IOUT = 2 mA		 18 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF (see (3)) 375 mVpp
IOUT Output current 0 4 mA
PG Power-good threshold
(fraction of nominal output voltage)		 VBIAS rising 86%
VBIAS falling 66%
RDIS Output discharge resistor Active when rail is disabled 100 Ω
COUT Output capacitor Recommended value (output capacitors for VOFS / VBIAS must be equal) 110 220 nF
tDISCHARGE < 40 µs at 2.9 V 100 110
VRST REGULATOR
VRST Output voltage –14 V
DC output voltage accuracy IOUT = 2 mA –3% 3%
DC load regulation VIN = 3.6 V, IOUT = 0 to 2 mA 13 V/A
DC line regulation VINA, VINL, VINR, VINC 2.7 to 6 V,
IOUT = 2 mA		 –21 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF (see (3)) 375 mVpp
VREF_VRST Reference voltage 500 mV
IOUT Output current 0 4 mA
PG Power-good threshold (fraction of nominal output voltage) VRST rising 90%
VRST falling 90%
RDIS Output discharge resistor Active when rail is disabled ±150 Ω
COUT Output capacitor 110 220 nF
tDISCHARGE < 70 µs at VBAT ≥ 2.7 V 100 110
LED DRIVER
VLED BUCK-BOOST
VLED Output voltage range 1.2 5.5 V
Default output voltage SW4, SW5, SW6 in OPEN position 3.5
VOVP Output overvoltage protection Clamps buck-boost output 5.5 7 V
VLED_OVP Fault detection threshold Triggers VLED_OVP interrupt 5.4 V
ISW Switch current limit 3.5 4.0 4.5 A
RDS(ON) MOSFET ON-resistance Switch A (from VINL to L1) 50 mΩ
Switch B (from L1 to PGNDL) 50
Switch C (from L2 to PGNDL) 50
Switch D (from L2 to VLED) 50
ƒSW Switching frequency 2.25 MHz
COUT Output capacitance 2 × 22 µF
RGB STROBE CONTROLLER SWITCHES
RDS(ON) Drain-source ON-resistance SW4, SW5, SW6 30 75 mΩ
ILEAK OFF-state leakage current VDS = 5.0 V 1 µA
LED CURRENT CONTROL
Vf LED forward voltage 4.8 V
ILED DLPA2000 LED currents VIN ≥ 2.3 V, VLED ≤ 4.8 V
RLIM = 100 mΩ, 0.1%, TA = 25°C (see register settings)
Current at minimum code 0x00Ch for SWx IDAC[9:0].		 25 mA
VIN ≥ 2.3 V, VLED ≤ 4.8 V
RLIM = 100 mΩ, 0.1%, TA = 25°C (see register settings)
Current at maximum code 0x307h for SWx_IDAC[9:0].		 750
DC current accuracy, SW4, 5, 6 RLIM = 100 mΩ 25 mA
Transient LED current limit range ILIM[3:0] = 0000 at RLIM = 100 mΩ 130 mA
ILIM[3:0] = 1111 at RLIM = 100 mΩ 1500
trise Current rise time ILED from 5% to 95%, ILED = 300 mA,
Transient current limit disabled
Not tested in production		 50 µs
1.1-V REGULATOR
VCORE (BUCK)
VIN Input voltage 2.3 6 V
VOUT Nominal fixed output voltage 1.1 V
DC output voltage accuracy 0 mA ≤ IOUT ≤ 600 mA at VIN > 2.5 V
VOUT = 1.1 V 		–1.5% 1.5%
d Maximum duty cycle 100%
RDS(ON) Low-side MOSFET on-resistance VIN = 3.6 V, TJ = 27ºC 185 380 mΩ
High-side MOSFET on-resistance 240 480 mΩ
IOUT Output current VIN > 2.3 V 300 600 mA
ILIMIT Switch current limit 1 A
TSS Soft-start time Time to ramp from 10% to 90% of VOUT,
VIN = 3.6 V		 250 µs
COUT Output capacitance 10 µF
L Nominal Inductance 2.2 µH
LOAD SWITCH
VIN Input voltage range LS_IN 1.8 3.6 V
RDS(ON) P-channel MOSFET on-resistance VIN = 1.8 V, over full temperature range 385 505 mΩ
COUT Output capacitor Ceramic 4.7 10 12 µF
ESR of output capacitor Ceramic 5 20 500 mΩ
MEASUREMENT SYSTEM (AFE)
G Amplifier gain (PGA) AFE_GAIN[1:0] = 01 1.0 V/V
AFE_GAIN[1:0] = 10 9.5
AFE_GAIN[1:0] = 11 18
VOFS Input referred offset voltage PGA, AFE_CAL_DIS = 1
Not tested in production		 –1 1 mV
Comparator
Not tested in production		 –1.5 1.5
tsettle Settling time To 1% of final value
(not tested in production)		 15 µs
To 0.1% of final value
(not tested in production)		 52
ƒsample Sampling rate Not tested in production 19 kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL Output low-level IO = 0.5-mA sink current
(RESETZ, CMP_OUT)		 0 0.3 V
IO = 5-mA sink current
(SPI_DOUT, INTZ)		 0 0.3 × VSPI
VOH Output high-level IO = 0.5-mA source current
(RESETZ, CMP_OUT)		 1.3 2.5 V
IO = 5-mA source current
(SPI_DOUT)		 0.7 × VSPI VSPI
VIL Input low-level PROJ_ON, LED_SEL0, LED_SEL1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI
VIH Input high-level PROJ_ON, LED_SEL0, LED_SEL1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI VSPI
IBIAS Input bias current VIO = 3.3 V, any input pin 0.5 µA
tDEGLITCH Deglitch time PROJ_ON,
(not tested in production)		 1 ms
LED_SEL0, LED_SEL1 pins
(not tested in production)		 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA = –30 to 85°C –10% 10%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
MOTOR DRIVER
POWER SUPPLY
VINM Operating motor supply voltage 2 6 V
IM Operating motor current 500(4) mA
H-BRIDGE FETS
RDS(ON) HS + LS FET on resistance VV2V5 = 2.5 V, VM = 3 V, IO = 200 mA,
TJ = 25°C		 1.9 2.1 Ω
IOFF Off-state leakage current ±200 nA
MOTOR DRIVER PROTECTION CIRCUITS
IOCP Overcurrent protection trip level per A-out or B-out pin 0.53 1.16 A
tTSD Thermal shutdown temperature Die temperature 150 160 180 °C
(1) Fully functional but limited parametric performance
(2) Including rectifying diode
(3) To reduce ripple the COUT can be increased. VRIPPLE is inversely proportional to COUT.
(4) Power dissipation and thermal limits must be observed