DLPS227A october   2021  – june 2023 DLPA300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Control Logic
    6. 6.6  5-V Linear Regulator
    7. 6.7  Bias Voltage Boost Converter
    8. 6.8  Reset Voltage Buck-Boost Converter
    9. 6.9  VOFFSET Regulator
    10. 6.10 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Linear Regulator
      2. 7.3.2 Bias Voltage Boost Converter
      3. 7.3.3 Reset Voltage Buck-Boost Converter
      4. 7.3.4 VOFFSET Regulator
      5. 7.3.5 Serial Communications Port (SCP)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection Guidelines
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Rail Guidelines
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding Guidelines
    2. 10.2 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PFP|80
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Design Requirements

For the correct operation of a display system based on the 9-μm pixel family of DMDs, the DLPA300 micromirror driver must be controlled by the DLPC4420 or DLPC4430 display controller. The embedded software in the DLPC4430 or DLPC4420 display controller coordinates the video data to the DMD and the bias, offset and reset waveforms created by the DLPA300 micromirror driver that are input to the MBRST pins on the DMD. This results in the highest possible image quality and system efficiency.

The key design requirements are power supply sequencing for power up and power down. The 9-μm family of DMDs require that the VCC2 supply be turned on after the 1.8-V supply is full on and stable. Similarly, on power down, the DMDs require that the VCC2 supply be full off before the 1.8-V supply is begins its power off ramp.

The DLPA300 micromirror driver imparts one power supply sequencing constraint. Because VRESET is generated by an external supply, the DLPC4430 display controller cannot control this supply directly by software. Therefore, it is necessary to use the VBIAS supply to control the power up and power down of the external VRESET power supply.

These power supply sequencing requirements necessitate external circuitry to control the VRESET and VCC2 power supply sequencing, as seen in Figure 8-1.