DLPS052A October   2015  – September 2023 DLPA3000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Parameters
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply and Monitoring
        1. 8.3.1.1 Supply
        2. 8.3.1.2 Monitoring
          1. 8.3.1.2.1 Block Faults
          2. 8.3.1.2.2 Low Battery and UVLO
          3. 8.3.1.2.3 Auto LED Turn Off Functionality
          4. 8.3.1.2.4 Thermal Protection
      2. 8.3.2 Illumination
        1. 8.3.2.1 Programmable Gain Block
        2. 8.3.2.2 LDO Illum
        3. 8.3.2.3 Illumination Driver A
        4. 8.3.2.4 RGB Strobe Decoder
          1. 8.3.2.4.1 Break Before Make (BBM)
          2. 8.3.2.4.2 Openloop Voltage
          3. 8.3.2.4.3 Transient Current Limit
        5. 8.3.2.5 Illumination Monitoring
          1. 8.3.2.5.1 Power Good
          2. 8.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 8.3.2.6 Load Current and Supply Voltage
        7. 8.3.2.7 Illumination Driver Plus Power FETS Efficiency
      3. 8.3.3 DMD Supplies
        1. 8.3.3.1 LDO DMD
        2. 8.3.3.2 DMD HV Regulator
          1. 8.3.3.2.1 Power-Up and Power-Down Timing
        3. 8.3.3.3 DMD/DLPC Buck Converters
        4. 8.3.3.4 DMD Monitoring
          1. 8.3.3.4.1 Power Good
          2. 8.3.3.4.2 Overvoltage Fault
      4. 8.3.4 Buck Converters
        1. 8.3.4.1 LDO Bucks
        2. 8.3.4.2 General Purpose Buck Converters
        3. 8.3.4.3 Buck Converter Monitoring
          1. 8.3.4.3.1 Power Good
          2. 8.3.4.3.2 Overvoltage Fault
        4. 8.3.4.4 Buck Converter Efficiency
      5. 8.3.5 Auxiliary LDOs
      6. 8.3.6 Measurement System
      7. 8.3.7 Digital Control
        1. 8.3.7.1 SPI
        2. 8.3.7.2 Interrupt
        3. 8.3.7.3 Fast-Shutdown in Case of Fault
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application Setup Using DLPA3000
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical Application with DLPA3000 Internal Block Diagram
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 SPI Connections
    4. 11.4 RLIM Routing
    5. 11.5 LED Connection
    6. 11.6 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Support Resources
    8. 12.8 Electrostatic Discharge Caution
    9. 12.9 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over operating free-air temperature range. VIN = 12 V, TA = 0 to +70°C, typical values are at TA = 25°C, configuration according to Typical Applications (VIN =12 V, IOUT = 6 A, LED, internal FETs) (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLIES
INPUT VOLTAGE
VIN Input voltage range VINA – pin 6(5) 12 20 V
VLOW_BAT Low battery warning threshold VINA falling (through a 5-bit trim function) 3.9 18.4 V
Hysteresis VINA rising 90 mV
VUVLO(6) UVLO threshold VINA falling (through a 5-bit trim function) 3.9 6.22 18.4 V
Hysteresis VINA rising 90 mV
VSTARTUP Startup voltage DMD_VBIAS, DMD_VOFFSET, DMD_VRESET loaded with 10 mA 6 V
INPUT CURRENT
IIDLE Idle current IDLE mode, all VIN pins combined 15 µA
ISTD Standby current STANDBY mode, analog, internal supplies and LDOs enabled, DMD, ILLUMINATION and BUCK CONVERTERS disabled 3.7 mA
IQ_DMD Quiescent current (DMD) Quiescent current DMD block (in addition to ISTD), VINA + DRST_VIN 0.49 mA
IQ_ILLUM Quiescent current (ILLUM) Quiescent current ILLUM block (in addition to ISTD) in 6 A LED configuration, internal FETs, V_openloop= 3 V (, VINA + ILLUM_VIN + ILLUM_A_VIN + ILLUM_B_VIN 21 mA
IQ_BUCK Quiescent current
(per BUCK)		 Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 1 V 4.3 mA
Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 5 V 15
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 1 V 0.41
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 5 V 0.46
IQ_TOTAL Quiescent current (Total) Typical Application: 6 A LED, Internal FETs, DMD. ACTIVE mode, all VIN pins combined, DMD, ILLUMINATION and PWR1,2 enabled, PWR3,4,5,6,7 disabled 38 mA
INTERNAL SUPPLIES
VSUP_5P0V Internal supply, analog 5 V
VSUP_2P5V Internal supply, logic 2.5 V
DMD—LDO DMD
VDRST_VIN 6 12 20 V
VDRST_5P5V 5.5 V
PGOOD Power good DRST_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection DRST_5P5V 7.2 V
Regulator dropout At 25 mA, VDRST_VIN = 5.5 V 56 mV
Regulator current limit(1) 300 340 400 mA
DMD—REGULATOR
RDS(ON) MOSFET ON-resistance Switch A (from DRST_5P5V to DRST_HS_IND) 920 mΩ
Switch B (from DRST_LS_IND to DRST_PGND) 450
VFW Forward voltage drop Switch C (from DRST_LS_IND to DRST_VBIAS(1)), VDRST_LS_IND = 2 V, IF = 100 mA 1.21 V
Switch D (from DRST_LS_IND to DRST_VOFFSET(1)), VDRST_LS_IND = 2 V, IF = 100 mA 1.22
tDIS Rail Discharge time COUT= 1 µF 40 µs
tPG Power-good timeout Not tested in production 15 ms
ILIMIT Switch current limit 610 mA
VOFFSET REGULATOR
VOFFSET Output voltage 10 V
DC output voltage accuracy IOUT= 10 mA –0.3 0.3 V
DC Load regulation IOUT= 0 mA to 10 mA –10 V/A
DC Line regulation IOUT= 10 mA, DRST_VIN = 8 V to 20 V –5 mV/V
VRIPPLE Output ripple IOUT= 10 mA, COUT= 1 µF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VOFFSET rising 86%
VOFFSET falling 66%
C Output capacitor Recommended value(4) (use same value as output capacitor on VRESET) 1 µF
tDISCHARGE <40 µs at VIN = 8 V 1
VBIAS REGULATOR
VBIAS Output voltage 18 V
DC output voltage accuracy IOUT= 10 mA –0.3 0.3 V
DC Load regulation IOUT= 0 mA to 10 mA –18 V/A
DC Line regulation IOUT = 10 mA, DRST_VIN = 8 V to 20 V –3 mV/V
VRIPPLE Output ripple IOUT= 10 mA, COUT = 470 nF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VBIAS rising 86%
VBIAS falling 66%
C Output capacitor Recommended value (use same or smaller value as output capacitors VOFFSET / VRESET) 470 nF
tDISCHARGE < 40 µs at VIN = 8 V 470
VRESET REGULATOR
VRST Output voltage –14 V
DC output voltage accuracy IOUT= 10 mA –0.3 0.3 V
DC Load regulation IOUT= 0 mA to 10 mA –4 V/A
DC Line regulation IOUT = 10 mA, DRST_VIN = 8 V to 20 V –2 mV/V
VRIPPLE Output ripple IOUT= 10 mA, COUT= 1 µF 120 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold 90%
C Output capacitor Recommended value(4) (use same value as output capacitor on VOFFSET) 1 µF
tDISCHARGE <40 µs at VIN = 8 V 1
DMD—BUCK CONVERTERS
OUTPUT VOLTAGE
VPWR_1_VOUT Output Voltage 1.1 V
VPWR_2_VOUT Output Voltage 1.8 V
DC output voltage accuracy IOUT= 0 mA –3% 3%
MOSFET
RON,H High side switch resistance 25°C, VPWR_1,2_Boost – VPWR1,2_SWITCH = 5.5 V 150 mΩ
RON,L Low side switch resistance(1) 25°C 85 mΩ
LOAD CURRENT
Allowed load current(2) 3 A
IOCL Current limit(1) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(MIN) Minimum off time(1) TA = 25°C, VFB = 0 V 270 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
ILLUMINATION—LDO ILLUM
VILLUM_VIN 6 12 20 V
VILLUM_5P5V 5.5 V
PGOOD Power good ILLUM_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection ILLUM_5P5V 7.2 V
Regulator dropout At 25 mA, VILLUM_VIN = 5.5 V 53 mV
Regulator current limit(1) 300 340 400 mA
ILLUMINATION—DRIVER A,B
VILLUM_A,B_IN Input supply voltage range 6 12 20 V
PWM
ƒSW Oscillator frequency 3 V < VIN < 20 V 600 kHz
tDEAD Output driver dead time HDRV off to LDRV on, TRDLY = 0 28 ns
HDRV off to LDRV on, TRDLY = 1 40
LDRV off to HDRV on, TRDLY = 0 35
MAXIMUM CURRENTS
HSD OC High-side drive over current Internal switches, IDS threshold, single buck
(6 A use case)		 9.5 A
LSD MC Low-side drive maximum allowed current Both directions In or Out. Internal switches, IDS threshold, single buck
(6 A use case)		 9.5 A
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.75 V
PGOOD
RatioUV Undervoltage protection 89%
POWER FETs
RON Power FETs High-Side,TA = 25°C, VILLUM_A,B_BOOST – ILLUM_A,B_SW = 5.5 V 150 mΩ
Low-side, TA= 25°C 85
LED CURRENT CONTROL
VLED_ANODE LED anode voltage(1) Ratio with respect to VILLUM_A,B_VIN
(Duty cycle limitation)		 0.85x
7.2 V
ILED LED currents VILLUM_A,B_VIN ≥ 8 V. See register SWx_IDAC[9:0] (Register Maps) for settings. 300 6000 mA
DC current offset, CH1,2,3_SWITCH RLIM = 25 mΩ –75 0 75 mA
Transient LED current limit range (programmable) 20% higher than ILED. Min-setting,
RLIM= 25 mΩ		 0.67 A
20% higher than ILED. Max-setting,
RLIM= 25 mΩ		 8
tRISE Current rise time ILED from 5% to 95%, ILED = 300 mA, transient current limit disabled(1) 50 µs
BUCK CONVERTERS—LDO_BUCKS
VPWR_VIN Input voltage range PWR1,2,5,6,7_VIN 6 12 20 V
VPWR_5P5V PWR_5P5V 5.5 V
PGOOD Power good PWR_5P5V Rising 80%
Falling 60%
OVP Overvoltage Protection PWR_5P5V 7.2 V
Regulator dropout At 25 mA, VPWR_VIN= 5.5 V 41 mV
Regulator current limit(1) 300 340 400 mA
BUCK CONVERTER—GENERAL PURPOSE BUCK CONVERTER(7)
OUTPUT VOLTAGE
VPWR6_VOUT Output voltage (General purpose buck2) 8-bit programmable 1 5 V
DC output voltage accuracy IOUT= 0 mA –3.5% 3.5%
MOSFET
RON,H High side switch resistance 25°C, VPWR6_Boost – VPWR6_SWITCH = 5.5 V 150 mΩ
RON,L Low side switch resistance(1) 25°C 85 mΩ
LOAD CURRENT
Allowed load current PWR6(2) 2 A
IOCL Current limit(1)(2) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(MIN) Minimum off time(1) TA = 25°C, VFB = 0 V 270 310 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
AUXILIARY LDOs
VPWR3,4_VIN Input voltage range LDO1 (PWR4), LDO2 (PWR3) 3.3 12 20 V
PGOOD Power good PWR3,4_VOUT PWR3,4_VOUT rising 80%
PWR3,4_VOUT falling 60%
OVP Overvoltage protection PWR3,4_VOUT 7 V
DC output voltage accuracy PWR3,4_VOUT IOUT= 0 mA –3% 3%
Regulator current limit(1) 300 340 400 mA
tON Turn-on time to 80% of VOUT = PWR3 and PWR4, C= 1 µF 40 µs
LDO2 (PWR3)
VPWR3_VOUT Output voltage PWR3_VOUT 2.5 V
Load current capability 200 mA
DC load regulation PWR3_VOUT VOUT = 2.5 V, IOUT= 5 mA to 200 mA –70 mV/A
DC line regulation PWR3_VOUT VOUT = 2.5 V, IOUT= 5 mA, PWR3_VIN = 3.3 to 20 V 30 µV/V
LDO1 (PWR4)
VPWR4_VOUT Output voltage PWR4_VOUT 3.3 V
Load current capability 200 mA
DC load regulation PWR4_VOUT VOUT = 3.3 V, IOUT= 5 mA to 200 mA –70 mV/A
DC line regulation PWR4_VOUT VOUT = 3.3 V, IOUT= 5 mA, PWR4_VIN= 4 to 20 V 30 µV/V
Regulator dropout At 25 mA, VOUT= 3.3 V, VPWR4_VIN= 3.3 V 48 mV
MEASUREMENT SYSTEM
LABB
τRC Settling time To 1% of final value(1) 4.6 6.6 µs
To 0.1% of final value(1) 7 10
VACMPR_IN_LABB Input voltage range ACMPR_IN_LABB 0 1.5 V
Sampling window ACMPR_IN_LABB Programmable per 7 µs 7 28 µs
DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS
VSPI_VIN SPI supply voltage range SPI_VIN 1.7 3.6 V
VOL Output low-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3 mA sink current 0 0.3 V
SPI_DOUT. IO = 5 mA sink current 0 0.3 × VSPI_VIN
INT_Z. IO = 1.5 mA sink current 0 0.3 × VSPI_VIN
VOH Output high-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3 mA source current 1.3 2.5 V
SPI_DOUT. IO = 5 mA source current 0.7 × VSPI_VIN VSPI_VIN
VIL Input low-level PROJ_ON, CH_SEL_0, CH_SEL_1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI_VIN
VIH Input high-level PROJ_ON, CH_SEL_0, CH_SEL_1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI_VIN VSPI_VIN
IBIAS Input bias current VIO= 3.3 V, any digital input pin 0.1 µA
SPI_CLK SPI clock frequency(3) Normal SPI mode, DIG_SPI_FAST_SEL = 0, ƒOSC = 9 MHz 0 36 MHz
Fast SPI mode, DIG_SPI_FAST_SEL = 1, VSPI_VIN> 2.3 V, ƒOSC = 9 MHz 20 40
tDEGLITCH Deglitch time CH_SEL_0, CH_SEL_1(1) 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA= 0 to 70°C –5% 5%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Not production tested
(2) Take care to not exceed the max power dissipation. Refer to Section 11.6.
(3) Maximum depends linearly on oscillator frequency fOSC.
(4) Take care that the capacitor has the specified capacitance at the related voltage, that is, VOFFSET, VBIAS, or VRESET.
(5) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA3000 to fully operate. While 6.0 V is the min VIN voltage supported, TI recommends that the UVLO is never set below 6.21 V for fault fast power down. 6.21 V gives margin above 6.0 V to protect against the case where someone suddenly removes VIN’s power supply, which causes the VIN voltage to drop rapidly. Failure to keep VIN above 6.0V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut down can result in permanent damage to the DMD. Since 6.21 V is .21 V above 6.0 V, when UVLO trips there is time for the DLPA3000 and DLPC343x to park the DMD mirrors and do a fast shut down of supplies VOFS, VRST, and VBIAS. For whatever UVLO setting is used, if VIN’s power supply is suddenly removed enough bulk capacitance should be included on VIN inside the projector to keep VIN above 6.0 V for at least 100 μs after UVLO trips.
(6) UVLO should not be used for normal power down operation, it is meant as a protection from power loss.
(7) General purpose buck2 (PWR6) is currently supported.