DLPS071A October   2015  – February 2023 DLPA3005

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Parameters
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Description
    3. 7.3 Feature Description
      1. 7.3.1 Supply and Monitoring
        1. 7.3.1.1 Supply
        2. 7.3.1.2 Monitoring
          1. 7.3.1.2.1 Block Faults
          2. 7.3.1.2.2 Auto LED Turn Off Functionality
          3. 7.3.1.2.3 Thermal Protection
      2. 7.3.2 Illumination
        1. 7.3.2.1 Programmable Gain Block
        2. 7.3.2.2 LDO Illumination
        3. 7.3.2.3 Illumination Driver A
        4. 7.3.2.4 RGB Strobe Decoder
          1. 7.3.2.4.1 Break Before Make (BBM)
          2. 7.3.2.4.2 Openloop Voltage
          3. 7.3.2.4.3 Transient Current Limit
        5. 7.3.2.5 Illumination Monitoring
          1. 7.3.2.5.1 Power Good
          2. 7.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 7.3.2.6 Illumination Driver plus Power FETs Efficiency
      3. 7.3.3 External Power FET Selection
        1. 7.3.3.1 Threshold Voltage
        2. 7.3.3.2 Gate Charge and Gate Timing
        3. 7.3.3.3 RDS(ON)
      4. 7.3.4 DMD Supplies
        1. 7.3.4.1 LDO DMD
        2. 7.3.4.2 DMD HV Regulator
        3. 7.3.4.3 DMD/DLPC Buck Converters
        4. 7.3.4.4 DMD Monitoring
          1. 7.3.4.4.1 Power Good
          2. 7.3.4.4.2 Overvoltage Fault
      5. 7.3.5 Buck Converters
        1. 7.3.5.1 LDO Bucks
        2. 7.3.5.2 General Purpose Buck Converter
        3. 7.3.5.3 Buck Converter Monitoring
          1. 7.3.5.3.1 Power Good
          2. 7.3.5.3.2 Overvoltage Fault
        4. 7.3.5.4 Buck Converter Efficiency
      6. 7.3.6 Auxiliary LDOs
      7. 7.3.7 Measurement System
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 Interrupt
      3. 7.5.3 Fast-Shutdown in Case of Fault
      4. 7.5.4 Protected Registers
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection for General-Purpose Buck Converters
      3. 8.2.3 Application Curve
    3. 8.3 System Example With DLPA3005 Internal Block Diagram
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up and Power-Down Timing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 SPI Connections
      2. 10.1.2 RLIM Routing
      3. 10.1.3 LED Connection
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

To connect the 0.47 1080 DMD (DLP4710), two DLPC3439s, and DLPA3005, see the reference design schematic. When a circuit board layout is created from this schematic a very small circuit board is possible. An example small board layout is included in the reference design data base. Layout guidelines should be followed to achieve reliable projector operation. The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical OEM who specializes in designing optics for DLP projectors.

The component selection of the buck converter is mainly determined by the output voltage. Table 8-1 shows the recommended value for inductor LOUT and capacitor COUT for a given output voltage.

Table 8-1 Recommended Buck Converter LOUT and COUT
VOUT (V)LOUT (µH) COUT (µF)
MINTYPMAXMIN MAX
1 – 1.51.52.24.72268
1.5 – 3.32.23.34.72268
3.3 – 53.34.72268

The inductor peak-to-peak ripple current, peak current and RMS current can be calculated using Equation 8, Equation 9 and Equation 10 respectively. The inductor saturation current rating must be greater than the calculated peak current. Likewise, the RMS or heating current rating of the inductor must be greater than the calculated RMS current. The switching frequency of the buck converter is approximately 600 kHz (ƒSWITCH).

Equation 8. GUID-DEA626EA-9373-40BB-8D8B-32CA89CE1436-low.gif
Equation 9. GUID-C9255F03-2EB6-46F5-B893-BD33B9A780A0-low.gif
Equation 10. GUID-EE46CC5C-2A2A-4B0D-95E5-B8F4FC74F556-low.gif

The capacitor value and ESR determines the level of output voltage ripple. The buck converter is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22 to 68 μF. Equation 11 can be used to determine the required RMS current rating for the output capacitor.

Equation 11. GUID-D9E0D2A1-07CF-4A6C-8397-EED621E27CF3-low.gif

Two other components need to be selected in the buck converter configuration. The value of the input-capacitor (pin PWRx_VIN) should be equal or greater than halve the selected output capacitance COUT. In this case CIN 2 × 10 µF is sufficient. The capacitor between PWRx_SWITCH and PWRx_BOOST is a charge pump capacitor to drive the high side FET. The recommended value is 100 nF.

Since the switching edges of the buck converter are relatively fast, voltage overshoot and ringing can become a problem. To overcome this problem a snubber network is used. The snubber circuit consists of a resistor and capacitor that are connected in series from the switch node to ground. The snubber circuit is used to damp the parasitic inductances and capacitances during the switching transitions. This circuit reduces the ringing voltage and also reduces the number of ringing cycles. The snubber network is formed by RSNx and CSNx. More information on controlling switch-node ringing in synchronous buck converters and configuring the snubber can be found in Analog Applications Journal.