DLPS240A June   2024  – August 2024 DLPA3085

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Parameters
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Description
    3. 6.3 Feature Description
      1. 6.3.1 Supply and Monitoring
        1. 6.3.1.1 Supply
        2. 6.3.1.2 Monitoring
          1. 6.3.1.2.1 Block Faults
          2. 6.3.1.2.2 Auto LED Turn-Off Functionality
          3. 6.3.1.2.3 Thermal Protection
      2. 6.3.2 Illumination
        1. 6.3.2.1 Programmable Gain Block
        2. 6.3.2.2 LDO Illumination
        3. 6.3.2.3 Illumination Driver A
        4. 6.3.2.4 RGB Strobe Decoder
          1. 6.3.2.4.1 Break Before Make (BBM)
          2. 6.3.2.4.2 Openloop Voltage
          3. 6.3.2.4.3 Transient Current Limit
        5. 6.3.2.5 Illumination Monitoring
          1. 6.3.2.5.1 Power Good
          2. 6.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 6.3.2.6 Illumination Driver Plus Power FETs Efficiency
      3. 6.3.3 External Power FET Selection
        1. 6.3.3.1 Threshold Voltage
        2. 6.3.3.2 Gate Charge and Gate Timing
        3. 6.3.3.3 RDS(ON)
      4. 6.3.4 DMD Supplies
        1. 6.3.4.1 LDO DMD
        2. 6.3.4.2 DMD HV Regulator
        3. 6.3.4.3 DMD/DLPC Buck Converters
        4. 6.3.4.4 DMD Monitoring
          1. 6.3.4.4.1 Power Good
          2. 6.3.4.4.2 Overvoltage Fault
      5. 6.3.5 Buck Converters
        1. 6.3.5.1 LDO Bucks
        2. 6.3.5.2 General Purpose Buck Converters
        3. 6.3.5.3 Buck Converter Monitoring
          1. 6.3.5.3.1 Power Good
          2. 6.3.5.3.2 Overvoltage Fault
        4. 6.3.5.4 Buck Converter Efficiency
      6. 6.3.6 Auxiliary LDOs
      7. 6.3.7 Measurement System
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 Interrupt
      3. 6.5.3 Fast-Shutdown in Case of Fault
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Component Selection for General-Purpose Buck Converter
      3. 7.2.3 Application Curve
    3. 7.3 System Example With DLPA3085 Internal Block Diagram
  9. 8 Power Supply Recommendations
    1. 8.1 Power-Up and Power-Down Timing
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 SPI Connections
      2. 9.1.2 RLIM Routing
      3. 9.1.3 LED Connection
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Power-Up and Power-Down Timing

The power-up and power-down sequence is important to ensure the correct operation of the DLPA3085 and to prevent damage to the DMD. The DLPA3085 controls the correct sequencing of the DMD_VRESET, DMD_VBIAS, and DMD_VOFFSET to ensure a reliable operation of the DMD.

The general startup sequence of the supplies is described in Supply and Monitoring. The power-up sequence of the high voltage DMD lines is especially important to not damage the DMD. Avoid a too-large delta voltage between DMD_VBIAS and DMD_VOFFSET, which could cause damage.

After PROJ_ON is pulled high, the DMD buck converters and LDOs are powered (PWR1-4) the DMD high voltage lines (HV) are sequentially enabled. First, DMD_VOFFSET is enabled. After a delay, DMD_VBIAS is enabled. Finally, after another delay DMD_VRESET is enabled. Now the DLPA3085 is fully powered and ready for starting projection.

For power down there are two sequences, normal power down (Figure 8-1) and a fault fast power down used in case a fault occurs (Figure 8-2).

In normal power-down mode, the power-down is initiated after pulling the PROJ_ON pin low. 25ms after PROJ_ON is pulled low, first DMD_VBIAS and DMD_VRESET stop regulating. 10ms later, DMD_VOFFSET will stop regulating. When DMD_VOFFSET stopped regulating, RESET_Z is pulled low. 1ms after the DMD_VOFFSET stops regulating, all other supplies are turned off. INT_Z remains high during the power-down sequence since no fault occurred. During power down it is ensured that the HV levels do not violate the DMD specifications on these three lines. For this, it is important to select the capacitors such that CVOFFSET is equal to CVRESET and CVBIAS is ≤ CVOFFSET, CVRESET.

The fast power-down mode (Figure 8-2) is started in case a fault occurs (INT_Z is pulled low), for instance, due to overheating. The fast power-down mode can be enabled or disabled through Main Status register (0x01), bit 7, FAST_SHUTDOWN_EN. By default, the mode is enabled. After the fault occurs, the regulation of DMD_VBIAS and DMD_VRESET is stopped. There is 540µs default delay time between fault and stop of regulation. After the regulation stops, there is a 4µs default delay time before all three DMD_VRESET, DMD_VBIAS, and DMD_VOFFSET high voltages lines are discharged and RESET_Z is pulled low.

Now the DLPA3085 is in a standby state. It remains in a standby state until the fault resolves. In case the fault resolves a restart is initiated. It starts then by powering up PWR_3 and follows the regular power-up as depicted in Figure 8-2. Again, for proper discharge timing/levels, the capacitors should be selected such that CVOFFSET is equal to CVRESET and CVBIAS is ≤ CVOFFSET, CVBIAS.

DLPA3085 Power Sequence Normal Shutdown Mode
  1. Arrows indicate the sequence of events automatically controlled by the digital state machine. Other events are initiated under SPI control.
  2. SUP_5P0V and SUP_2P5V rise to a precharge level with SYSPWR and reach the full level potential after PROJ_ON is pulled high.
Figure 8-1 Power Sequence Normal Shutdown Mode
DLPA3085 Power Sequence Fault Fast Shutdown Mode
  1. Arrows indicate the sequence of events automatically controlled by the digital state machine. Other events are initiated under SPI control.
  2. SUP_5P0V and SUP_2P5V rise to a precharge level with SYSPWR and reach the full level potential after PROJ_ON is pulled high.
Figure 8-2 Power Sequence Fault Fast Shutdown Mode