DLPS240A June   2024  – August 2024 DLPA3085

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Parameters
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Description
    3. 6.3 Feature Description
      1. 6.3.1 Supply and Monitoring
        1. 6.3.1.1 Supply
        2. 6.3.1.2 Monitoring
          1. 6.3.1.2.1 Block Faults
          2. 6.3.1.2.2 Auto LED Turn-Off Functionality
          3. 6.3.1.2.3 Thermal Protection
      2. 6.3.2 Illumination
        1. 6.3.2.1 Programmable Gain Block
        2. 6.3.2.2 LDO Illumination
        3. 6.3.2.3 Illumination Driver A
        4. 6.3.2.4 RGB Strobe Decoder
          1. 6.3.2.4.1 Break Before Make (BBM)
          2. 6.3.2.4.2 Openloop Voltage
          3. 6.3.2.4.3 Transient Current Limit
        5. 6.3.2.5 Illumination Monitoring
          1. 6.3.2.5.1 Power Good
          2. 6.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 6.3.2.6 Illumination Driver Plus Power FETs Efficiency
      3. 6.3.3 External Power FET Selection
        1. 6.3.3.1 Threshold Voltage
        2. 6.3.3.2 Gate Charge and Gate Timing
        3. 6.3.3.3 RDS(ON)
      4. 6.3.4 DMD Supplies
        1. 6.3.4.1 LDO DMD
        2. 6.3.4.2 DMD HV Regulator
        3. 6.3.4.3 DMD/DLPC Buck Converters
        4. 6.3.4.4 DMD Monitoring
          1. 6.3.4.4.1 Power Good
          2. 6.3.4.4.2 Overvoltage Fault
      5. 6.3.5 Buck Converters
        1. 6.3.5.1 LDO Bucks
        2. 6.3.5.2 General Purpose Buck Converters
        3. 6.3.5.3 Buck Converter Monitoring
          1. 6.3.5.3.1 Power Good
          2. 6.3.5.3.2 Overvoltage Fault
        4. 6.3.5.4 Buck Converter Efficiency
      6. 6.3.6 Auxiliary LDOs
      7. 6.3.7 Measurement System
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 Interrupt
      3. 6.5.3 Fast-Shutdown in Case of Fault
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Component Selection for General-Purpose Buck Converter
      3. 7.2.3 Application Curve
    3. 7.3 System Example With DLPA3085 Internal Block Diagram
  9. 8 Power Supply Recommendations
    1. 8.1 Power-Up and Power-Down Timing
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 SPI Connections
      2. 9.1.2 RLIM Routing
      3. 9.1.3 LED Connection
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information

THERMAL METRIC(1) DLPA3085 UNIT
PFD (HTQFP)
100 PINS
RθJA Junction-to-ambient thermal resistance(2) 7.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 0.7 °C/W
RθJB Junction-to-board thermal resistance N/A °C/W
ψJT Junction-to-top characterization parameter(4) 0.6 °C/W
ψJB Junction-to-board characterization parameter(5) 3.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, but since the device is intended to be cooled with a heatsink from the top case of the package, the simulation includes a fan and heatsink attached to the DLPA3085. The heatsink is a 22mm × 22mm × 12mm aluminum pin fin heatsink with a 12mm × 12mm × 3mm stud. The base thickness is 2mm and the pin diameter is 1.5 mm with an array of 6 × 6 pins. The heatsink is attached to the DLPA3085 with 100μm thick thermal grease with 3 W/m-K thermal conductivity. The fan is 20 × 20 × 8mm with 1.6cfm open volume flow rate and 0.22-inch water pressure at stagnation.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the fan and heatsink described in note 2.
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the fan and heatsink described in note 2.