DLPS240A June   2024  – August 2024 DLPA3085

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Parameters
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Description
    3. 6.3 Feature Description
      1. 6.3.1 Supply and Monitoring
        1. 6.3.1.1 Supply
        2. 6.3.1.2 Monitoring
          1. 6.3.1.2.1 Block Faults
          2. 6.3.1.2.2 Auto LED Turn-Off Functionality
          3. 6.3.1.2.3 Thermal Protection
      2. 6.3.2 Illumination
        1. 6.3.2.1 Programmable Gain Block
        2. 6.3.2.2 LDO Illumination
        3. 6.3.2.3 Illumination Driver A
        4. 6.3.2.4 RGB Strobe Decoder
          1. 6.3.2.4.1 Break Before Make (BBM)
          2. 6.3.2.4.2 Openloop Voltage
          3. 6.3.2.4.3 Transient Current Limit
        5. 6.3.2.5 Illumination Monitoring
          1. 6.3.2.5.1 Power Good
          2. 6.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 6.3.2.6 Illumination Driver Plus Power FETs Efficiency
      3. 6.3.3 External Power FET Selection
        1. 6.3.3.1 Threshold Voltage
        2. 6.3.3.2 Gate Charge and Gate Timing
        3. 6.3.3.3 RDS(ON)
      4. 6.3.4 DMD Supplies
        1. 6.3.4.1 LDO DMD
        2. 6.3.4.2 DMD HV Regulator
        3. 6.3.4.3 DMD/DLPC Buck Converters
        4. 6.3.4.4 DMD Monitoring
          1. 6.3.4.4.1 Power Good
          2. 6.3.4.4.2 Overvoltage Fault
      5. 6.3.5 Buck Converters
        1. 6.3.5.1 LDO Bucks
        2. 6.3.5.2 General Purpose Buck Converters
        3. 6.3.5.3 Buck Converter Monitoring
          1. 6.3.5.3.1 Power Good
          2. 6.3.5.3.2 Overvoltage Fault
        4. 6.3.5.4 Buck Converter Efficiency
      6. 6.3.6 Auxiliary LDOs
      7. 6.3.7 Measurement System
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 Interrupt
      3. 6.5.3 Fast-Shutdown in Case of Fault
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Component Selection for General-Purpose Buck Converter
      3. 7.2.3 Application Curve
    3. 7.3 System Example With DLPA3085 Internal Block Diagram
  9. 8 Power Supply Recommendations
    1. 8.1 Power-Up and Power-Down Timing
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 SPI Connections
      2. 9.1.2 RLIM Routing
      3. 9.1.3 LED Connection
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2.3 Illumination Driver A

The illumination driver of the DLPA3085 is a buck controller for driving two external low-ohmic N-channel FETs (Figure 6-4). The theory of operation of a buck converter is explained in the application note Understanding Buck Power Stages in Switchmode Power Supplies (SLVA057). For proper operation, the selection of the external components is very important, especially the inductor LOUT and the output capacitor COUT. For best efficiency and ripple performance, an inductor and capacitor should be chosen with low equivalent series resistance (ESR). Set the voltage rating of the capacitor equal or greater than two times of the applied voltage across the capacitor in the application.

DLPA3085 Typical Illumination Driver Configuration Figure 6-4 Typical Illumination Driver Configuration

Several factors determine the component selection of the buck converter, such as input voltage (SYSPWR), desired output voltage (VLED), and the allowed output current ripple. Configuration starts with selecting the inductor LOUT.

The value of the inductance of a buck power stage is selected such that the peak-to-peak ripple current flowing in the inductor stays within a certain range. Here, the target is set to have an inductor current ripple, kI_RIPPLE, less than 0.3 (30%). The minimum inductor value can be calculated given the input and output voltage, output current, switching frequency of the buck converter (ƒSWITCH= 600kHz), and inductor ripple of 0.3 (30%):

Equation 1. DLPA3085

Example: VIN= 12V, VOUT= 4.3V, IOUT= 16A results in an inductor value of LOUT= 1µH.

Once the inductor is selected, the output capacitor COUT can be determined. The value is calculated using the fact that the frequency compensation of the illumination loop has been designed for an LC-tank resonance frequency of 15kHz:

Equation 2. DLPA3085

Example: COUT= 110µF given that LOUT= 1µH. A practical value is 2 × 68µF. Here, a parallel connection of two capacitors is chosen to lower the ESR even further.

The selected inductor and capacitor determine the output voltage ripple. The resulting output voltage ripple VLED_RIPPLE is a function of the inductor ripple kI_RIPPLE, output current IOUT, switching frequency ƒSWITCH, and the capacitor value COUT:

Equation 3. DLPA3085

Example: kI_RIPPLE= 0.3, IOUT= 16A, ƒSWITCH= 600kHz and COUT= 2 x 68µF results in an output voltage ripple of VLED_RIPPLE= 7mVpp

As can be seen, this is a relatively small ripple.

It is strongly advised to keep the capacitance value low. The larger the capacitor value the more energy is stored. In case of a VLED going down stored energy needs to be dissipated. This might result in a large discharge current. For a VLED step down from V1 to V2, while the LED current was I1. The theoretical peak reverse current is:

Equation 4. DLPA3085

Depending on the selected external FETs, the following three components might need to be added for each power FET:

  • Gate series resistor (RG)
  • Gate series diode (DG)
  • Gate parallel capacitance (CG)

It is advisable to have placeholders for these components in the board design.

The gate series resistors can slow down the enable transient of the power FET. Since large currents are being switched, a fast transient implies a potential risk of ringing. Slowing down the turn-on transient reduces the edge steepness of the drain current and thus reduces the induced inductive ringing. A resistance of a few Ohms typically is sufficient.

The gate series resistance is also present in the turn-off transient of the power FET. This might have a negative effect on the non-overlap timing. To keep the turn-off transient of the power FET fast, a parallel diode with the gate series resistance can be used. The cathode of the diode should be directed to the DLPA3085 device to have a fast gate pulldown.

A third component that might be needed, depending on the specific configuration and FET selection, is an extra gate-source filter capacitance. Specifically for the higher supply voltages, this capacitance is advisable. Due to a large drain voltage swing and the drain-gate capacitance, the gate of a disabled power FET might be pulled high parasitically.

For the low-side FET, this can happen at the end of the non-overlap time while the power converter supplies current. In that case, the switch node is low at the end of the non-overlap time. Enabling the high-side FET pulls high the switch node. Due to the large and steep switch node edge, the charge is being injected via the drain-gate capacitance of the low-side FET into the gate of the low-side FET. As a result, the low-side FET can be enabled for a short period of time causing a shoot-through current.

For the high-side FET a dual case exists. If the power converter is discharging VLED, the power converter current is directed inward and thus at the end of the non-overlap time the switch node is high. If at that moment the low-side FET is enabled, via the gate-drain capacitance of the high-side FET charge is being injected into the gate of the high-side FET potentially causing the device to switch on for a short amount of time. That will cause a shoot-through current as well.

To reduce the effect of the charge injection via the drain-gate capacitance, an extra gate-source filter capacitance can be used. Assuming a linear voltage division between gate-source capacitance and gate-drain capacitance, for a 20V supply voltage the ratio of gate-source capacitance and gate-drain capacitance should be kept to about 1:10 or larger. It is advised to carefully test the gate-drive signals and the switch node for potential cross-conduction.

Sometimes dual FETs are used to spread out power dissipation (heat). In order to prevent parasitic gate-oscillation a structure as shown in Figure 6-5 is suggested. Each gate is being isolated with RISO to damp potential oscillations. A resistance of 1 Ohm is typically sufficient.

DLPA3085 Using RISO to Prevent Gate Oscillations When Using Power FETs in ParallelFigure 6-5 Using RISO to Prevent Gate Oscillations When Using Power FETs in Parallel

Finally, two other components need to be selected in the buck converter. The value of the input capacitor (pin ILLUM_A_VIN) should be equal or greater than the selected output capacitance COUT, in this case ≥2 × 68µF. The capacitor between ILLUM_A_SWITCH and ILLUM_A_BOOST is a charge pump capacitor to drive the high-side FET. The recommended value is 100nF.