For switching power supplies, the layout is an important step in the design, especially when it concerns high peak currents and high switching frequencies. If the layout is not done carefully, the regulator could show stability issues and EMI problems. Therefore, use wide and short traces for high current paths and their return power ground paths. For the DMD HV regulator, place the input capacitor, output capacitor, and the inductor as close as possible to the IC. To minimize ground noise coupling between different buck converters, separate their grounds and connect them at a central point under the part. For the DMD HV regulator, the recommended value for the capacitors is 1µF for VRST and VOFS, and 470nF for VBIAS. The inductor value is 10µH.

The high currents of the buck converter concentrate around pins VIN, SWITCH, and PGND (Figure 9-1). The voltage at the pins VIN, PGNDm and FB are DC voltages while the pin SWITCH has a switching voltage between VIN and PGND. In case the FET between pins 63 – 64 is closed, the red line indicates the current flow while the blue line indicates the current flow when the FET between pins 62 – 63 is closed.

These paths carry the highest currents and must be kept as short as possible.

For the LDO DMD, use a 1µF capacitor in parallel with a 10µF capacitor on the input and a 10µF capacitor on the output of the LDO. Make the voltage rating of the capacitor equal to or greater than two times the applied voltage across the capacitor in the application.

For LDO bucks, use a 1µF capacitor on the input and a 10µF capacitor on the output of the LDO. Make the voltage rating of the capacitor equal to or greater than two times the applied voltage across the capacitor in the application.

Figure 9-1 High AC Current Paths in a Buck Converter

The trace to the VIN pin carries high AC currents; therefore, the trace should be low resistive to prevent a voltage drop across the trace. Additionally, place the decoupling capacitors as close to the VIN pin as possible.

The SWITCH pin is connected alternately to the VIN or GND. This means a square wave voltage is present on the SWITCH pin with an amplitude of VIN, and containing high frequencies. This can lead to EMI problems if not properly handled. To reduce EMI problems, place a snubber network (RSN6 and CSN6) at the SWITCH pin to prevent and suppress unwanted high-frequency ringing at the moment of switching.

The PGND pin sinks a high current. Connect the PGND pin to a star ground point so it does not interfere with other ground connections.

The FB pin is the sense connection for the regulated output voltage, which is a DC voltage; no flows through this pin. The voltage on the FB pin is compared with the internal reference voltage to control the loop. Make the FB connection at the load so that the I•R drop does not affect the sensed voltage.