DLPS096B November 2017 – May 2022 DLPC120-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PIN | I/O | I/O | CLOCK | ||
---|---|---|---|---|---|
NAME | NO. | POWER | TYPE | SYSTEM | DESCRIPTION |
MEM_CLK | F2 | 1.80 V | Os | N/A | DDR memory, Differential Memory Clock. |
MEM_CLKZ | F1 | ||||
MEM_A0 | H1 | Os | MEM_CLK | DDR memory, Multiplexed Row and Column Address. | |
MEM_A1 | C1 | ||||
MEM_A2 | F4 | ||||
MEM_A3 | D2 | ||||
MEM_A4 | H2 | ||||
MEM_A5 | G1 | ||||
MEM_A6 | G2 | ||||
MEM_A7 | G3 | ||||
MEM_A8 | F3 | ||||
MEM_A9 | E1 | ||||
MEM_A10 | B1 | ||||
MEM_A11 | D1 | ||||
MEM_A12 | E2 | ||||
MEM_BA0 | J1 | Os | MEM_CLK | DDR memory, Bank Select. | |
MEM_BA1 | J2 | ||||
MEM_RASZ | D3 | Os | MEM_CLK | DDR memory, Row Address Strobe (Active low). | |
MEM_CASZ | J3 | Os | MEM_CLK | DDR memory, Column Address Strobe (Active low). | |
MEM_WEZ | C2 | Os | MEM_CLK | DDR memory, Write Enable (Active low). | |
MEM_CSZ | K2 | Os | MEM_CLK | DDR memory, Chip Select (Active low). | |
MEM_CKE | K1 | Os | MEM_CLK | DDR memory, Clock Enable (Active high). | |
MEM_ODT | E4 | Os | MEM_CLK | DDR memory, On die termination (ODT). ODT is not verified and supported operational mode. This pin should be left open or connected to corresponding DDR2 pin. | |
MEM_RST | C3 | Os | MEM_CLK | DDR memory, Reset. Do Not connect. | |
MEM_ZQ | J4 | Os | MEM_CLK | DDR memory, External pad where to connect the external impedance calibration resistor. The user connects the PAD pin through an external 240 Ω ± 1% resistor to ground. | |
MEM_DQS0 | N1 | BSD | N/A | DDR memory, Lower Byte, R/W Data Strobe. | |
MEM_DQSZ0 | N2 | BSD | N/A | DDR memory, Lower Byte, R/W Data Strobe, inverted. | |
MEM_DQ0 | P2 | Bs | MEM_DQS0 | DDR memory, Lower Byte, Bidirectional R/W Data. | |
MEM_DQ1 | R1 | ||||
MEM_DQ2 | P1 | ||||
MEM_DQ3 | M2 | ||||
MEM_DQ4 | L3 | ||||
MEM_DQ5 | M1 | ||||
MEM_DQ6 | L2 | ||||
MEM_DQ7 | L1 | ||||
MEM_DQS1 | R4 | 1.80 V | Bs | N/A | DDR memory, Upper Byte, R/W Data Strobe. |
MEM_DQSZ1 | T4 | BSD | N/A | DDR memory, Upper Byte, R/W Data Strobe, inverted. | |
MEM_DQ8 | T6 | Bs | MEM_DQS1 | DDR memory, Upper Byte, Bidirectional R/W Data. | |
MEM_DQ9 | R6 | ||||
MEM_DQ10 | T5 | ||||
MEM_DQ11 | R5 | ||||
MEM_DQ12 | P5 | ||||
MEM_DQ13 | T3 | ||||
MEM_DQ14 | T2 | ||||
MEM_DQ15 | R3 |