DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2 Design for Test Functions

The DLPC120-Q1 has several built-in test features. These tests can be run to verify ASIC functionality on startup or during normal operation. Refer to DLPC120-Q1 Programmer's Guide for more detail regarding test usage. Table 7-2 defines the execution time of each test.

Table 7-2 Test Execution Times
TEST NAMELENGTH (ms)SUMMARY
DDR2 BIST (Short)145The Short DDR2 BIST implements a memory check using a March13 Algorithm to verify the external DDR2 SDRAM frame buffer space. It runs at power-up or also can be executed on demand, but it is recommended to run only at power-up, since the image will flash if executed on demand. The short version runs a portion of the long test. 
DDR2 BIST (Long)470The Long DDR2 BIST is the same as the Short DDR2 BIST, but it runs the test multiple times.
FLASH BIST (1 MByte)215The Flash BIST calculates configuration memory checksum (32 bits) for data integrity of the Flash data and interface. Flash checksum is recommended to be done at power-up to verify configuration settings. The Flash BIST memory range to perform checksum is programmable to up to 32M.
System BIST(2)See(1)The System BIST validates the DLPC120-Q1 internal logic. It sends a known test pattern image through the ASIC to verify the checksum at the last stage before the data reaches the DMD. When enabled, the checksum for each frame of data is calculated and stored in an I2C register.
DMD Interface Test6.93The DMD JTAG BIST validates the connection between the ASIC and DMD. It uses the DMD JTAG interface to sample the ASIC pins and compare against expected values, and it also tries to detect shorts between signals. The BIST is run on demand.
Front End Video ChecksumSee(1)The Front End Video Checksum is used to verify that the video is received correctly at the front end on the specified region of the frame. When enabled, it calculates the checksum for the specified region of the video frame and stored in an I2C register.
Video Detect TestSee(1)The Video Detect test shall be used to monitor external video VSYNC. If external video is not valid, the DMD must be put into a safe state (e.g. switched to an internal black test pattern).
(1) The length of these tests will vary depending on frame rate but will not exceed 2 frames.
(2) Some processing options must be turned off for this test.