DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 JTAG and DMD Interface Test

The DLPC120-Q1 has two test interfaces using JTAG protocol:

  • A standard JTAG (IEEE-1149) function of the ASIC is provided. The TI-provided BSDL file contains the details of the DLPC120-Q1 boundary scan chain. This JTAG interface is provided to enable system level validation of proper assembly of the DLPC120-Q1 onto a PCB.
  • The DLPC120-Q1's DMD interface is designed to be the controller for an in-system DMD interface test. The DMD interface should be connected directly to the DMD's JTAG pins. This interface is exclusively designed and verified to support the DLP3030-Q1, DLP3020-Q1 and DLP3021-Q1.

GUID-984D50B5-7C39-4146-AC3B-58BB1219EC7B-low.gifFigure 8-2 JTAG and DMD Interface Test

Using the DMD JTAG function, the DMD interface signals are toggled, and the connection at the DMD is verified by using the DMD JTAG signals to sample the inputs, and then toggled back to the DLPC120-Q1 for comparison to expected values. All DMD logic signals, except DAD OEZ, are tested individually for stuck high or low independently. Alternating data pattern for adjacent pins, as well as "walking 1’s" and "walking 0’s" patterns are used during the test. The DAD_OEZ is only tested in the high state as asserting this signal and toggling the inputs could cause damage to the DMD. Refer to Figure 8-3 for recommended connections for the DLPC120-Q1 boundary scan test configuration. Refer to Figure 8-4 for recommended connections of the DLPC120-Q1 to DMD interface test. For additional information about the DMD Boundary scan function refer to the specific DMD device datasheet.

GUID-C31436E5-6328-4063-A834-D7B379E9B9F9-low.gifFigure 8-3 DLPC120-Q1 JTAG Boundary Scan Connection Example
GUID-128CF408-4912-4385-9349-3804C9B91351-low.gifFigure 8-4 DLPC120-Q1 JTAG to DMD Interface Connection Example