DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 DMD Interface

PINI/OI/OCLOCK
NAMENO.POWERTYPESYSTEMDESCRIPTION
DMD_D0B121.80 VO5DMD_DCLKDMD data pins. DMD data pins are DDR (Double Data Rate) signals that are clocked on both edges of DMD_DCLK.
DMD_D1A13
DMD_D2A12
DMD_D3B11
DMD_D4C10
DMD_D5A11
DMD_D6D9
DMD_D7B10
DMD_D8A10
DMD_D9B9
DMD_D10A9
DMD_D11A8
DMD_D12B8
DMD_D13C8
DMD_D14A7
DMD_DCLKA6O5N/ADMD data clock (DDR)
DMD_LOADBC7O5DMD_DCLKDMD data load signal (active low)
DMD_SCTRLB6O5DMD_DCLKDMD data serial control signal
DMD_TRCB7O5DMD_DCLKDMD data toggle rate control
DMD_DAD_OEZA5O5AsyncDMD DAD output enable (active low). A pullup (10 kΩ to 100 kΩ) to the 1.8-V rail for the DMD interface is needed to keep this signal inactive when tristated. 
DMD_DAD_BUSB5O5DMD_SAC_CLKDMD DAD bus data
DMD_DAD_STRBD7O5DMD_DCLKDMD DAD bus strobe.
DMD_SAC_BUSA4O5DMD_SAC_CLKDMD SAC bus data
DMD_SAC_CLKA3O5N/ADMD SAC bus clock
DMD_JTCKB4O4N/ADMD interface test clock. Signal connected to DMD JTAG interface to allow the verification of the interface. The interface is tristated when not active.
DMD_JTMSC5O4N/ADMD interface test mode. Signal connected to DMD JTAG interface to allow the verification of the interface. The interface is tristated when not active.
DMD_JTDID5O4N/ADMD interface test data output.  Signal connected to DMD JTAG interface to allow the verification of the interface. This signal connects to the DMD JTAG TDI. The interface is tristated when not active.
DMD_JTDOC4I1N/ADMD interface test data input. Signal connected to DMD JTAG interface to allow the verification of the interface. This signal connects to the DMD JTAG TDO. Internal pulldown.
DMD_PWR_ENC113.30 VO6AsyncDMD power regulator enable (active high)