DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Serial Flash Interface

The DLPC120-Q1 utilizes an external SPI serial flash memory device for configuration support. The minimum required size is dependent on the desired minimum number of Sequences, CMT tables, and Splash options, while the maximum supported size is 64 Mb. The DLPC120-Q1 can be used to Read, Erase, and program the serial flash.  Refer to DLPC120-Q1 Programmer's Guide for details of Flash configuration information.

The DLPC120-Q1 utilizes a single SPI interface, employing SPI mode 0 protocol, operating at a frequency of 39.0 MHz. All read operations assume the Flash supports address auto-incrementing.  The DLPC120-Q1 should support any flash device that meets these criteria plus the criteria listed in Table 8-1.

Table 8-1 SPI Flash Instruction Op Code Compatibility Requirements
FLASH COMMANDOPCODE
Fast Read (Single Output)0x0B
Read Electronic Signature0xAB
OthersMay vary

The DLPC120-Q1 does not have any specific Page, Block or Sector size requirements. If the user would like to use a portion of the serial flash for storing external data (such as calibration data) via the I2C interface, then the minimum sector size needs to be considered as it will drive minimum erase size. Note that use of serial flash for storing external data may impact the number of features that can be supported.

The DLPC120-Q1 does not drive the /HOLD (active low Hold) or /WP (active low Write Protect) pins on the flash device and thus these pins should be tied to a logic high on the PCB via an external pull-up. 

Table 8-2 DLPC120-Q1 Compatible SPI Flash Device Options
VENDORPART NUMBERDENSITY (Mb)SUPPLY VOLTAGE SUPPORTED(1)
ISSIIS25LP064A-JMLE643.3 V
WinbondW25Q64CVSFAG643.3 V
SpansionS25FL064P0XMFV000643.3 V
MicronM25P64-VMF3TPB643.3 V
(1) The Flash supply voltage must match VCCIO_2 on the DLPC120-Q1. Multiple voltage options are often available under the same base part number.